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preliminary this document contains in f o r mation on a product under d e v elopment at ad v anced micro d e vice s . the in f o r mation is intended to help y ou e v aluate this product . amd rese r v es the r ight to change or discontinue wo r k on this proposed product without notic e . pu b lication# 17881 r e v : c amendment/ 0 issue date : january 1998 1 AM79C90 cmos local area net w ork cont r oller f or ethernet (c-lance) distinctive char a cteristics n compatible with ethernet and ieee 802.3 10 b ase- 5 t ype a , and 10 b ase- 2 t ype b , ?heapernet , 10 b ase-t n easi l y interfaced with 80x86 , 680x0 , am29000 a , z8000 mic r op r ocesso r s n on-boa r d dma and b uffer management , 64- b yte receive , 48- b yt e t ransmit fifos n 24-bit-wide linear addressing (bus master mode) n net w ork and pa c ket er r or repo r ting n ba c k-to-ba c k pa c ket reception with as little as 0.5 m s interframe spacing n diagnostic routines inte r nal/ e xte r nal loopba c k crc logic che c k time domain re?ctometer n l o w p o wer consumption f or p o we r -sensitive applications n complete l y software- and ha r d ware-compatible with amd s lance d e vice (am7990) (see appendix a) general description the AM79C90 cmos local area net w o r k controller f or ethe r net (c-lance) is a 48-pi n vlsi d e vice de- signed to greatly simplify inter f acing a microcomputer or minicomputer to an ieee 802.3/ethernet local area net w o r k . the c-lance, in conjunction with the am7992b serial inter f ace adapter (sia), am7996 or am79c98 and am79c10 0 t ranscei v e r , and closely coupled local memo r y and microprocesso r , is intended to pr o vide the user with a complete inter f ace module f or an ethe r net netwo r k . the AM79C90 is designed using a scala b le cmos technology and is compati b le with a v a r iety of microprocessor s . on-board dma, ad v anced b uf f er management, and e xtensi v e error repo r ting and diagnostics f acilitate design and impr o v e system per f o r manc e . block di a gram intr hold hld a ale/as cs adr d as d alo d ali read bm 0/byte bm 1/b usak o read y reset p a rallel bus inter f ace dma/data p ath control microprogram store c-lance/ cpu control bus inter f ace station address detection ret r y logic se r ial i/o inter f ace a23:16 rx rclk tx tclk clsn tena rena d al15:0 local cpu interf ace 17881c-1 am7992b sia interf ace
amd p r e l i m i n a r y 2 AM79C90 related amd products part no. description am7996 ieee 802.3/ethernet/cheapernet tap transceiver am79c100 twisted-pair ethernet transceiver plus (tpex+) AM79C900 integrated local area communications controller tm (ilacc tm ) am79c940 media access controller for ethernet (mace tm ) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa single-chip ethernet controller (with microsoft a plug n play support) am79c965 pcnet-32 single-chip 32-bit ethernet controller (for 386dx, 486 and vl buses) am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c974 pcnet-scsi combination ethernet and scsi controller for pci systems am79c98 twisted-pair ethernet transceiver (tpex) am79c981 integrated multiport repeater plus tm (imr+ tm ) am79c987 hardware implemented management information base tm (himib tm ) connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v ss dal6 dal5 dal4 dal3 dal2 dal1 dal0 read intr dali dalo das bm 0/byte bm 1/ busako hold / busrq ale/ as hlda cs adr ready reset v ss v dd dal8 dal9 dal10 dal11 dal12 dal13 dal14 dal15 a16 a17 a18 a19 a20 a21 a22 a23 rx rena tx clsn rclk tena tclk dal7 17881b-2 17881b-3 note: pin 1 is marked for orientation. dip plcc 1 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 7 6 5 4 3 2 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 2 9 3 0 3 1 3 2 3 3 3 4 2 7 28 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 nc nc dal2 dal3 dal4 dal5 dal6 dal7 v ss v dd dal8 dal9 dal10 dal11 dal12 nc nc nc cs nc nc adr ready reset nc nc v ss tclk tena rclk clsn tx nc nc dal1 dal0 read intr dali dalo nc nc das bm 0/byte nc nc bm 1/busrq hold /b usrq ale/ as hlda nc nc nc dal13 dal14 dal15 a16 a17 a18 a19 nc nc a20 a21 a22 a23 rx rena
AM79C90 3 preliminary typical ethernet/cheapernet node aui?ttachment unit interface dte?ata terminal equipment mau?edium attachment unit local cpu local memo r y AM79C90 c-lance am7992b sia local bus t ypical ethernet 10 b ase-t node dte a ui ca b le am79c98 am79c100 t wisted- p air rg58a/u or rg58c/u bnc ? local cpu local memo r y AM79C90 c-lance am7992b sia p o wer supply local bus ethernet dte local bus cheapernet a ui ca b le m a u ethe r net coax t a p p o wer supply am7996 t ranscei v er am7996 t ranscei v er 17881c-4 dte local cpu local memo r y AM79C90 c-lance am7992b sia local cpu local memo r y AM79C90 c-lance am7992b sia local bus dte am79c98 am79c100 t wisted- p air p o wer supply m a u
4 AM79C90 preliminary ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list congurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of specic v alid combinations and to che c k on n e wly released combination s . AM79C90 p c device number/description AM79C90 cmos local area net w o r k controller f or ethe r net optional p r ocessing blan k = standard processing t r = tape and reel packaging oper a ting conditions c = commercial ( 0 c to +7 0 c) p a ck a g e type p = 48- pin plastic dip (pd 048) j = 68- pin plastic leaded chip carrier (pl 068) speed not applicable b v alid combinations AM79C90 p c , j c , jctr
AM79C90 5 preliminary pin description a16?23 high o r der a d dress bus (output , three- state) additional address bits to access a 24 - bit addres s . these lines are d r i v en as a bus master onl y . adr register address p o r t select (input) when the c-lance is a sl a v e , adr indicates which of the t w o register po r ts is selected . adr l o w selects register data po r t ; adr high selects register address po r t . adr m ust be v alid throughout the data po r tion of the b us cycle and is only used b y the c-lance when cs is l o w . ale/ as address latch enable (output , three- state) used to de m ultipl e x the d al lines and dene the address po r tion of the b us cycl e . this l/o pin is pro- g r amma b le through bit (01) of csr3. as ale (csr3 (01), a con = 0), the signal transitions from a high to a l o w du r ing the address po r tion of the t r ans f er and remains l o w du r ing the data po r tion. ale can be used b y a sl a v e d e vice to control a latch on the b us address line s . when ale is high, the latch is open, and when ale goes l o w , the latch is closed . a s as (csr3 (01), a con = 1), the signal pulses l o w du r ing the address po r tion of the b us t r ansaction . the l o w - to- hlgh transition of as can be used b y a sl a v e d e vice to strobe the address into a registe r . the c-lance d r i v es the ale/as line only as a bus maste r . bm 0/byte , bm 1 / b usak o (output , three- state) the t w o pins are pro g ramma b le through bit (00) of csr3. bm 0 , bm 1?f csr3 (00) bcon = 0 pin 15 = bm 0 (output , three- state) (48- pin dlps) pin 16 = bm 1 (output , three- state) (48- pin dlps) bm 0 , bm 1 (byte mask) . this indicates that the b yte(s) on the d al are to be read or w r itten du r ing this b us transaction . the c- lance d r i v es these lines only as a bus maste r . it ignores the byte mask lines when it is a bus sl a v e and assumes word trans f er s . byte selection using byte mask is done as desc r ibed b y the f oll o wing ta b le: byte, b usak o ?f csr3 (00) bcon = 1 pin 15 = byte (output , three- state) (48- pin dlps) pin 16 = b usak o (output) (48- pin dips) byte selection m a y also be done using the byte line and d al00 lin e , latched du r ing the address po r tion of the b us cycl e . the c-lance d r i v es byte only as a bus master and ignores it when a bus sl a v e selection is done (similar to bm 0, bm 1) . byte selection is done as outlined in the f oll o wing ta b le: b usak o is a b us request daisy chain output . if the chip is not requesting the b us and it recei v es hld a , b usak o will be d r i v en l o w . if the c-lance is re- questing the b us when it recei v es hld a , b usak o will remain high. byte swapping in order to be compati b le with the v a r iety of 16- bit mi- croprocessors a v aila b le to the designe r , the c-lance m a y be pro g rammed to s w ap the position of the upper- and l o wer-order b ytes on data i n v ol v ed in t r ans f ers with the inte r nal fifo s . byte s w apping is done when bswp = 1 . the most signi cant b yte of the w ord in this case will appear on d al lines 7? and the least signicant b yte on d al lines 15?. when byte = h (indicating a b yte t r ans f er) the ta b le in- dicates on which pa r t of the 16-bit data b us the actual data will appea r . when e v er b yte s w ap is acti v ated, the only data that is s w apped is data t r a v eling to and from th e t ransmit/ recei v e fifo s . bm 1 bm 0 selection l o w l o w whol e w ord l o w high upper byte hlgh l o w l o wer byte hlgh high none byte d al 00 selection l o w l o w whol e w ord l o w high illegal condition hlgh l o w l o wer byte hlgh high upper byte
6 AM79C90 preliminary clsn collision (input) a logical input that indicates that a collision is occur r ing on the channel. cs chip select (input) indicate s , when asse r ted, that the c-lance is the sl a v e d e vice of the data trans f e r . cs m ust be v alid throughout the data po r tion of the b us cycl e . cs m ust not be asse r ted when hld a is l o w . d al00 d al15 data/address lines (input/output , three- state) the time m ultipl e x ed address/data b u s . du r ing the ad- dress po r tion of a memo r y trans f e r , d al00 d al15 contains the l o wer 16 bits of the memo r y addres s . the upper 8 bits of address are contained in a16?23. du r ing the data po r tion of a memo r y t r ans f e r , d al00 d al15 contains the read or w r ite data, depending on the type of t r ans f e r . the c- lance d r i v es these lines as a bus master and as a bus sl a v e . d ali data/address line in (output , three- state) an e xte r nal b us t r anscei v er control lin e . d ali is as- se r ted when the c- lance reads from the d al line s . it will be l o w du r ing the data po r tion of a read trans f er and remain high f or the entire trans f er if it is a write. d ali is d r i v en only when c- lance is a bus maste r . d alo data/address line out (output , three- state) an e xte r nal b us transcei v er control lin e . d alo is as- se r ted when the c-lance d r i v es the d al line s . d alo will be l o w only du r ing the address po r tion if the t r ans- f er is a rea d . it will be l o w f or the entire trans f er if the t r ans f er is a write . d alo is d r i v en only when c- lance is a bus maste r . d as data st r obe (input/output , three- state) de nes the data po r tion of the b us transaction . d as is high during the address po r tion of a b us transaction and l o w du r ing the data po r tion . the l o w - to-hlgh tr ansition can be used b y a sl a v e d e vice to strobe b us data into a registe r . d as is d r i v en only as a bus maste r . hld a bus hold a c kn o wledge (input) a response to hold . when hld a is l o w in response to the chip s asse r tion of hold , the chip is the bus maste r . du r ing bus master ope r ation, the c-lance w aits f or hld a to be deasse r ted high be f ore reasse r ting hold l o w . this insures proper b us handsha k e under all situation s . hold / b usrq bus hold request (output , open drain) asse r ted b y the c-lance when it requires access to memo r y . hold is held l o w f or the entire ensuing b us t r ansaction . the function of this pin is pro g rammed through bit (00) of csr3 . bit (00) of csr3 is cleared whe n reset is asse r ted . when csr3 (00) bcon = 0 pin 17 = hold (output open drain and input sense) (48-pin dips) when csr3 (00) bcon = 1 pin 17 = b usrq (i/o sens e , open d r ain) (48-pin dlps) if the c-lance w ants to use the b u s , it looks at hold / b usrq ; if it is high the c-lance can pull it l o w and request the b u s . if it is already l o w , the c-lance w aits f or it to go inacti v e-hlgh be f ore requesting the b u s . intr interrupt (output , open drain) an attention signal that indicate s , when acti v e , that one or more of the f oll o wing csr0 status ags is set : babl, merr, mis s , rin t , tint or idon . intr is ena b led b y bit 06 of csr0 (inea = 1) . intr remains asse r ted until the source of inter r upt is rem o v ed. rclk receive clo c k (input) a 10 mhz square w a v e synchroni z ed to the recei v e data and only acti v e while receiving an input bit stream . signal line mode bits bswp = 0 and bcon = 1 bswp = 1 and bcon = 1 byte = l and d al00 = l w ord w ord byte = l and d al00 = h illegal illegal byte = h and d al00 = h upper byte l o wer byte byte = h and d al00 = l l o wer byte upper byte
AM79C90 7 preliminary read (input/output , three- state) indicates the type of operation to be per f o r med in the current b us cycl e . this signal is an output when the c- lance is a bus maste r . hig h data is ta k en off the d al lines b y the c- lance . l o w data is placed on the d al lines b y the c- lance. the signal is an input when the c - lance is a bus sl a v e . hig h data is placed on the d al lines b y the c- lance . l o w data is ta k en off the d al lines b y the c- lance . read y (input/output , open drain) when the c - lance is a bus maste r , read y is an asynchronous a c kn o wledgment from the b us memo r y that it will accept data in a write cycle or that it has put data on the d al lines in a read cycl e . as a bus sl a v e , the c-lance asse r ts read y when it has put data on the d al lines du r ing a read cycle or is about to ta k e data off the d al lines du r ing a w r ite cycl e . read y is a response to d as and will retu r n high afte r d as has gone high . read y is an input when the c - lance is a bus master and an output when the c- lance is a bus sl a v e . rena receive ena b le (input) a logical input that indicates the presence of car r ier on the channel . reset reset (input) reset causes the c-lance to cease operation, clear its inte r nal logi c , f orce all three- state b uf f ers to the high- impedance stat e , and enter an idle state with the stop bit of csr0 set . it is recommended that a 3.3 k w pullup resistor be connected to this pin. rx receive (input) recei v e input bit stream. tclk t ransmit clo c k (input) 10 mhz clo c k. tena t ransmit ena b le (output) t r ansmit output bit stream ena b l e . when asse r ted, it ena b les v alid t r ansmit output (tx). tx t ransmit (output) t ransmit output bit stream. v dd p o wer supp l y pin + 5 v 5% it is recommended that 0.1 m f and 10 m f decoupling capacitors be used betwee n v dd an d v ss . v ss g r ound pin 1 and 24 (48 - pin dlps) should be connected together e xte r nall y , as close to the chip as possi b l e .
amd p r e l i m i n a r y 8 AM79C90 functional description the parallel interface of the cmos local area network controller for ethernet (c-lance) has been designed to be friendly or easy to interface to a variety of popular microprocessors. these microprocessors include the am29000, 80x86, 680x0, z8000 and lsi-11. the c-lance has a 24-bit wide linear address space when it is in the bus master mode. a programmable mode of operation allows byte addressing in one of two ways: a byte/word control signal compatible with the 80x86 and z8000 or an upper data strobe and lower data strobe signal compatible with microprocessors such as the 68000. a programmable polarity on the address strobe signal eliminates the need for external logic. the c-lance interfaces with both multiplexed and de- multiplexed data busses and features control signals for address/data bus transceivers. the c-lance is pin-for- pin compatible with amds lance device (am7990). please refer to appendix b for a complete comparison between the c-lance and lance devices. a16Ca23 dal0Cdal15 cpu ale buffer buffer data and address bits 0C15 address bits 16C23 control decoder buffer latch dal0Cdal1 5 a16Ca2 3 control ale a16Ca23 c-lance ale adr cs dal0 C dal15 a16Ca23 17881b-5 figure 1. c-lance/cpu interfacing multiplexed bus
p r e l i m i n a r y amd 9 AM79C90 latch buffer decode data/address bits 0-15 ale address bits 16-23 c-lance cs a0Ca23 a0Ca15 a16Ca23 17881b-6 data bus address bus figure 2. c-lance/cpu interfacing demultiplexed bus during initialization, the cpu loads the starting address of the initialization block into two internal control regis- ters. the c-lance has four internal control and status registers (csr0, 1, 2, 3) which are used for various functions, such as the loading of the initialization block address, and programming different modes and status conditions. the host processor communicates with the c-lance during the initialization phase, for demand transmission, and periodically to read the status bits fol- lowing interrupts. all other transfers to and from the memory are automatically handled as dma. interrupts to the microprocessor are generated by the c-lance upon: completion of its initialization routine the reception of a packet the transmission of a packet transmitter timeout error a missed packet memory error the cause of the interrupt is ascertained by reading csr0. bit (06) of csr0, (inea), enables or disables interrupts to the microprocessor. in systems where poll- ing is used in place of interrupts, bit (07) of csr0, (intr), indicates an interrupt condition. the basic operation of the c-lance consists of two dis- tinct modes: transmit and receive. in the transmit mode, the c-lance chip directly accesses data (in a transmit buffer) in memory. it prefaces the data with a preamble, start frame delimiter (sfd), and calculates and appends a 32-bit crc. on transmission, the first byte of data loads into the 48-byte transmit fifo; the c-lance then begins to transmit preamble while simultaneously loading the rest of the packet into transmit fifo for transmission. in the receive mode, packets are sent via the am7992b sla to the c-lance. the packets are loaded into the 64-byte receive fifo for preparation of automatic downloading into buffer memory. a crc is calculated and compared with the crc appended to the data pack- et. if the calculated crc does not agree with the packet crc, an error bit is set. addressing packets can be received using three different destina- tion addressing schemes: physical, logical and promiscuous. the first type is a full comparison of the 48-bit destina- tion address in the packet with the node address that was programmed into the c-lance during an initializa- tion cycle. there are two types of logical addresses. one is group type mask where the 48-bit address in the packet is put through a hash filter to map the 48-bit physical addresses into 1 of 64 logical groups. if any of these 64 groups have been preselected as the logical address, then the 48-bit address is stored in main mem- ory. at this time, a look up is performed by the host com- puter comparing the 48-bit incoming address with the pre-stored 48-bit logical address. this mode can be useful if sending packets to all of a particular type of de- vice simultaneously (i.e., send a packet to all file servers or all printer servers). additional details on logical ad- dressing can be found in the initialization section
amd p r e l i m i n a r y 1 0 AM79C90 under logical address filter. the second logical ad- dress is a broadcast address where all nodes on the net- work receive the packet. the last receive mode of operation is referred to as promiscuous mode in which a node will accept all packets on the medium regardless of their destination address. collision detection and implementation the ethernet and ieee 802.3 csma/cd network ac- cess algorithms are implemented completely within the c-lance. in addition to listening for a clear medium be- fore transmitting, ethernet handles collisions in a prede- termined way. should two transmitters attempt to seize the medium at the same time, they will collide and the data on the medium will be garbled. the transmitting nodes listen while they transmit, detect the collision, then continue to transmit for a predetermined length of time to jam the network and ensure that all nodes have recognized the collision. the transmitting nodes then delay a random amount of time according to the ether- net truncated binary backoff algorithm in order that the colliding nodes do not try to repeatedly access the net- work at the same time. the c-lance also offers a se- lectable modified backoff algorithm for better performance on busy networks. up to 16 attempts to ac- cess the network are made by the c-lance before re- porting an error due to excessive collisions. error reporting and diagnostics extensive error reporting is provided by the c-lance. error conditions reported relate either to the network as a whole or to individual data packets. network-related errors are recorded as flags in the csrs and are exam- ined by the cpu following interrupt. packet-related er- rors are written into descriptor entries corresponding to the packet. system errors include: babbling transmitter transmitter attempting to transmit more than 1518 bytes, excluding preamble and start frame delimiter collision collision detection circuitry nonfunctional missed packet insufficient buffer space memory timeout memory response failure packet-related errors: crc invalid data framing packet did not end on a byte boundary overflow/underflow indicates abnormal latency in servicing a dma request buffer insufficient buffer space available the c-lance performs several diagnostic routines which enhance the reliability and integrity of the system. these include a crc check and two loop back modes (internal/external). errors may be introduced into the system to check error detection logic. a time domain reflectometer is incorporated into the c-lance to aid system designers in locating faults in the ethernet physi- cal medium. shorts and opens manifest themselves in reflections which are sensed by the tdr.
p r e l i m i n a r y amd 1 1 AM79C90 initialization block transmit descriptor for 1st data buffer transmit descriptor for 2nd data buffer transmit descriptor for 3rd data buffer transmit descriptor for nth data buffer receive descriptor for 1st data buffer receive descriptor for 2nd data buffer receive descriptor for 3rd data buffer receive descriptor for nth data buffer transmit data buffer #1 transmit data buffer #2 transmit data buffer #3 transmit data buffer #n receive data buffer #1 receive data buffer #2 receive data buffer #3 receive data buffer #n transmit descriptor ring (4 words per entry) receive descriptor ring (4 words per entry) transmit data buffers receive data buffers 17881b-7 figure 2-1. c-lance/processor memory interface
amd p r e l i m i n a r y 1 2 AM79C90 address of receive buffer 1 buffer 1 status buffer 1 byte count buffer 1 message count 2 2 2 2 n n n n receive descriptor ring data packet 1 data packet 2 data packet n pointer to initialization block c-lance csr registers initialization block mode of operation physical address logical address filter pointer to receive ring number of receive entries (n) pointer to transmit ring number of transmit entries (m) address of transmit buffer 1 buffer 1 status buffer 1 byte count buffer 1 error status 2 2 2 2 m m m m transmit descriptor ring receive buffer transmit buffer data packet 1 data packet 2 data packet m 17881b-8 figure 2-2. c-lance memory management buffer management a key feature of the c-lance and its on-board dma channel is the flexibility and speed of communication between the c-lance and the host microprocessor through common memory locations. the basic organi- zation of the buffer management is a circular queue of tasks in memory called descriptor rings as shown in figures 2-1 and 2-2. there are separate descriptor rings to describe transmit and receive operations. up to 128 tasks may be queued up on a descriptor ring awaiting execution by the c-lance. each entry in a descriptor ring holds a pointer to a data memory buffer and an entry for the length of the data buffer. data buffers can be chained or cascaded to handle a long packet in multiple data buffer areas. the c-lance searches the descrip- tor rings in a lookahead manner to determine the next empty buffer in order to chain buffers together or to han- dle back-to-back packets. as each buffer is filled, th e own bit is reset, allowing the host processor to process the data in the buffer. c-lance interface csr bits such as acon, bcon and bswp are used for programming the pin functions used for different inter- facing schemes. for example, acon is used to pro- gram the polarity of the address strobe signal (ale/ as ). bcon is used for programming the pins, for handling either the byte/ word method for addressing word or- ganized, byte addressable memories where the byte signal is decoded along with the least significant ad- dress bit to determine upper or lower byte, or an explicit scheme in which two signals labeled as byte mask ( bm 0 and bm 1) indicate which byte is addressed. when
p r e l i m i n a r y amd 1 3 AM79C90 the byte scheme is chosen, the bm 1 pin can be used for performing the function busako . bcon is also used to program pins for different dma modes. in a daisy chain dma scheme, 3 signals are used ( busrq , hlda , busako ). in systems using a dma controller for arbitration, only hold and hlda are used. c-lance in bus slave mode the c-lance enters the bus slave mode wheneve r cs becomes active. this mode must be entered whenever writing or reading the four status control registers (csr0, csr1, csr2, and csr3) and the register ad- dress pointer (rap). rap and csr0 may be read or written to at anytime, but the c-lance must be stopped (by setting the stop bit in csr0) for csr1, csr2, and csr3 access. read sequence (slave mode) at the beginning of a read cycle, cs , read, and das are asserted. adr must be valid at this time. (if adr is a 1, the contents of rap are placed on the dal lines. otherwise the contents of the csr register addressed by rap are placed on the dal lines.) after the data on the dal lines become valid, the c-lance asserts ready , cs , read, das , and adr must remain stable throughout the cycle. refer to figure 3. write sequence (slave mode) this cycle is similar to the read cycle, except that during this cycle, read is not asserted (read is low). the dal buffers are tristated which configures these lines as inputs. the assertion of ready by c-lance indicates to the memory device that the data on the dal lines have been stored by c-lance in its appropriate csr register . cs , read, das , adr and dal 15:00 must re- main stable throughout the write cycle. refer to figur e 4. note : setting the stop bit in the c-lance will gener- ate a c-lance reset, which will cause all bus control output signals (including ready ) to float. to guarantee slave write timing when the stop bit is being set in csr0, the c-lance will latch the stop bit and will wait for the slave cycle to complete before resetting itself and floating the output signals. c-lance in bus master mode all data transfers from the c-lance in the bus master mode are timed by ale, das , and ready . the auto- matic adjustment of the c-lance cycle by the ready signal allows synchronization with variable cycle time memory due either to memory refresh or to dual port ac- cess. transfers are a minimum of 600 ns in length ex- cept for the first transfer of a bus mastership period in which the minimum is 700 ns. transfers can be in- creased in 10 0 ns increments.
amd p r e l i m i n a r y 1 4 AM79C90 dal0Cdal15 das read ready (output from c-lance) hold cs adr read data see note 1 note: 1. there are two types of delays which depend on which internal register is accessed. type 1 refers to access of csr0, csr3 and rap. type 2 refers to access of csr1 and csr2 which are longer than type 1 delay. 17881b-9 o.d. figure 3. bus slave read timing
p r e l i m i n a r y amd 1 5 AM79C90 dal0Cdal15 das read ready (output from c-lance) hold cs adr 17881b-10 write data o.d. figure 4. bus slave write timing read sequence (master mode) a read cycle is begun by placing a valid address on dal00 C dal15 and a16 C a23. the byte mask sig- nals are asserted to indicate a word, upper byte or lower byte memory reference. read indicates the type of cy- cle. ale or as is pulsed, and the trailing edge of either can be used to latch addresses. dal00 C dal15 go into a 3-state mode, and das falls low to signal the begin- ning of the memory access. the memory responds by placin g ready low to indicate that the dal lines have valid data. the c-lance then latches memory data on the rising edge of das , which in turn ends the memory cycle and ready returns high. refer to figure 5-1. the bus transceiver controls, dali and dalo , are used to control the bus transceivers. dali directs data toward the c-lance, and dalo directs data or addresses away from the c-lance. during a read cycle, dalo goes inactive before dali becomes active to avoid spiking of the bus transceivers. write sequence (master mode) the write cycle is similar to the read cycle except that the dal00 C dal15 lines change from containing ad- dresses to data after either ale or as goes inactive. after data is valid on the bus, das goes active. data to memory is held valid after das goes inactive. refer to figure 5-2.
amd p r e l i m i n a r y 1 6 AM79C90 tclk hold hlda a16Ca23 bm 0, bm 1 ale das ready dal0Cdal15 (read) dalo (read) dali (read) read (read) o.d. address, bm 0, bm 1 address data in 100 200 300 400 500 t1 t2 t3 t4 t5 t6 t wait 17881b-11 0 t0 600 700 figure 5-1. bus master read timing (single dma cycle)
p r e l i m i n a r y amd 1 7 AM79C90 tclk hold hlda a16Ca23 bm 0, bm 1 ale das ready dal0Cdal15 (write) dalo (write) dali (write) read (write) o.d. address, bm 0, bm 1 address data out 0 100 200 300 400 500 600 t1 t2 t3 t4 t5 t6 t wait 17881b-12 t0 700 figure 5-2. bus master write timing (single dma cycle)
amd p r e l i m i n a r y 1 8 AM79C90 differences between ethernet versions 1 and 2 a . version 2 specifies that the collision detect of the transceiver must be activated during the inter- packet gap time. b . version 2 specifies some network management functions, such as reporting the occurrence of colli- sions, retries and deferrals. c . version 2 specifies that when transmission is ter- minated, the differential transmit lines are driven to 0 volt differentially (half step). differences between ieee 802.3 and ethernet a . ieee 802.3 specifies a 2-byte length field rather than a type field. the length field (802.3) describes the actual amount of data in the frame. b . ieee 802.3 allows the use of a pad field in the data section of a frame, while ethernet specifies the minimum packet size at 64 bytes. the use of a pad allows the user to send and receive packets which have less than 46 bytes of data. a list of significant differences between ethernet and ieee 802.3 at the physical layer include the following: ieee 802.3 ethernet end of transmission half step full step (rev 1) state or half step (rev 2) common mode voltage 5.5 v 0 C +5 v common mode curren t less than 1 ma 1.6 ma 40% receive , collision input threshold 160 mv 175 mv fault protection 16 v 0 v
p r e l i m i n a r y amd 1 9 AM79C90 programming this section defines the control and status registers and the memory data structures required to program the AM79C90 (c-lance). programming the AM79C90 (c-lance) the AM79C90 (c-lance) is designed to operate in an environment that includes close coupling with local memory and microprocessor (host). the AM79C90 c-lance is programmed by a combination of registers and data structures resident within the c-lance and memory registers. there are four control and status registers (csrs) within the c-lance which are pro- grammed by the host device. once enabled, the c-lance has the ability to access memory locations to acquire additional operating parameters. the AM79C90 has the ability to do independent buffer management as well as transfer data packets to and from the ethernet. there are three memory structures accessed by the chip: initialization block12 words in contiguous mem- ory starting on a word boundary. it also contains the operating parameters necessary for device op- eration. the initialization block is comprised of: mode of operation physical address logical address mask location to receive and transmit descriptor rings number of entries in receive and transmit descriptor rings receive and transmit descriptor ringstwo ring structures, one for incoming and outgoing packets. each entry in the rings is 4 words long and each entry must start on a quadword boundary. the de- scriptor rings are comprised of: the address of a data buffer the length of that data buffer status information associated with the buffer data bufferscontiguous portions of memory reserved for packet buffering. data buffers may begin on arbitrary byte boundaries. in general, the programming sequence of the c-lance may be summarized as: program the c-lances csrs by a host device to locate an initialization block in memory. the byte control, byte address, and address latch enable modes are also defined here. the c-lance loads itself with the information con- tained within the initialization block. the c-lance accesses the descriptor rings for packet handling. control and status registers there are four control and status registers (csrs) on the chip. the csrs are accessed through two bus ad- dressable ports, an address port (rap) and a data port (rdp). accessing the control and status registers the csrs are read (or written) in a two step operation. the address of the csr to be accessed is written into the rap during a bus slave transaction. during a subse- quent bus slave transaction, the data being read from (or written into) the rdp is read from (or written into) the csr selected in the rap. once written, the address in rap remains unchanged until rewritten. to distinguish the data port from the address port, a dis- crete input pin is provided. adr input pin port l register data port (rdp) h register address port (rap) register data port (rdp) 0 15 csr data 17881b-13 bit name description 15:00 cs r data writing data into rdp writes the data into the csr selected in rap. read- ing the data from the rdp reads the data from the csr selected in rap. csr 1 , csr 2 and csr 3 are acces- sible only when the stop bit of csr 0 is set. if the stop bit is not set while at- tempting to access csr 1 , csr 2 or csr 3 , the c-lance will return ready, but a read operation will return undefined data. write op- eration is ignored.
amd p r e l i m i n a r y 20 AM79C90 register address port (rap) res csr 1:0 17881b-14 bit name description 15:02 res reserved. read as zeroes. write as zeroes. 01:00 csr(1:0) csr address select. read/write. selects the csr to be accessed through the rdp. rap is cleared by bu s reset . csr(1 :0) csr 00 csr 0 01 csr 1 10 csr 2 11 csr 3 control and status register definition control and status register 0 (csr0) err babl cerr miss merr rint tint idon init strt stop tdmd txon rxon inea intr the c-lance updates csr 0 by logical oring the pre- vious and present value of csr 0. 17881b-15 15 0 bit name description 15 err error summary is set by the oring of babl, cerr, miss and merr. err remains set as long as any of the error flags are true. err is read only; writing it has no ef- fect. it is cleared by bus reset , set- ting the stop bit, or clearing the individual error flags. bit name description 14 babl babble is a transmitter timeout er- ror. it indicates that the transmitter has been on the channel longer than the time required to send the maxi- mum length packet. babl is a flag which indicates ex- cessive length in the transmit buffer. it will be set after 1519 bytes have been transmitted, excluding pream- ble and start frame delimiter; the c-lance will continue to transmit until the whole packet is transmitted or until there is a failure before the whole packet is transmitted. when babl error occurs, an interrupt will be generated if inea = 1. babl is read/clear only and is set by the c-lance, and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit. 13 cerr collision error indicates that the collision input to the c-lance was not asserted during the trans- mission, nor within 4.0 m s after the transmit completed. the collision af- ter transmission is a transceiver test feature. this function is also known as heartbeat or sqe (signal quality error) test. cerr is read/clear only and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by re- set or by setting the stop bit. cerr error will not cause an inter- rupt to occur (intr = 0). 12 miss missed packet is set when the receiver loses a packet because it does not own any receive buffer, in- dicating loss of data. fifo overflow is not reported be- cause there is no receive ring entry in which to write status. when miss is set, an interrupt will be generated if inea = 1. miss is read/clear only, and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit.
p r e l i m i n a r y amd 21 AM79C90 bit name description 11 merr memory error is set when the c-lance is the bus master and has not received ready within 25.6 m s after asserting the address on the dal lines. when a memory error is detected, the receiver and transmitter are turned off (csr 0 , txon = 0, rxon = 0) and an interrupt is generated if inea = 1. merr is read/clear only, and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit. 10 rint receiver interrupt is set when the c-lance updates an en- try in the receive descriptor ring for the last buffer received or reception is stopped due to a failure. when rint is set, an interrupt is generated if inea = 1. rint is read/clear only, and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit. 09 tint transmitter interrupt is set when the c-lance updates an en- try in the transmit descriptor ring for the last buffer sent or transmission is stopped due to a failure. when tint is set, an interrupt is generated if inea = 1. tint is read/clear only and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit. 08 idon initialization done indicates that the c-lance has completed the initialization procedure started by setting the init bit. when idon is set, the c-lance has read the in- itialization block from memory and stored the new parameters. when idon is set, an interrupt is generated if inea = 1. idon is read/clear only, and is set by the c-lance and cleared by writing a 1 into the bit. writing a 0 has no effect. it is cleared by reset or by setting the stop bit. bit name description 07 intr interrupt flag is set by the oring of babl, miss, merr, rint, tint and idon. if inea = 1 and intr = 1, the intr pin will be low. intr is read only; writing this bit has no effect. intr is cleared by reset, by setting the stop bit, or by clearing the condition causing the interrupt. 06 inea interrupt enable allows the intr pin to be driven low when the interrupt flag is set. if inea = 1 and intr = 1, the intr pin will be low. if inea = 0, the intr pin will be high, regardless of the state of the inter- rupt flag. inea is read/write and cleared by reset or by setting the stop bit. inea can be set at any time, regard- less of the state of the stop bit. (reference appendix b). 05 rxon receiver on indicates that the re- ceiver is enabled. rxon is set when strt is set if drx = 0 in the mode register in the initialization block and the initialization block has been read by the c-lance by setting the init bit. rxon is cleared when idon is set from setting the init bit and drx = 1 in the mode register, or a mem- ory error (merr) has occurred. rxon is read only; writing this bit has no effect. rxon is cleared by reset or by setting the stop bit. 04 txon transmitter on indicates that the transmitter is enabled. txon is set when strt is set if dtx = 0 in the mode register in the initializa- tion block and the init bit has been set. txon is cleared when idon is set and dtx = 1 in the mode regis- ter, or an error, such as merr, uflo or buff, has occurred during transmission. txon is read only; writing this bit has no effect. txon is cleared by reset or by setting the stop bit.
amd p r e l i m i n a r y 22 AM79C90 bit name description 03 tdmd transmit demand, when set, causes the c-lance to access the transmit descriptor ring without waiting for the polltime interval to elapse. tdmd need not be set to transmit a packet; it merely hastens the c-lances response to a trans- mit descriptor ring entry insertion by the host. tdmd is write with one only and is cleared by the microcode after it is used. it may read as a 1 for a short time after it is written because the microcode may have been busy when tdmd was set. it is also cleared by reset or by setting the stop bit. writing a 0 in this bit has no effect. 02 stop stop disables the c-lance from all external activity when set and clears the internal logic. setting stop is the equivalent of asserting reset . the c-lance remains in- active and stop remains set until the strt or init bit is set. if strt, init and stop are all set together, stop will override the other bits and only stop will be set. stop is read/write with one only and set by reset. writing a 0 to this bit has no effect. stop is cleared by setting either init or strt. csr 3 must be reloaded when the stop bit is set. 01 strt start enables the c-lance to send and receive packets, perform direct memory access, and do buffer management. the stop bit must be set prior to setting the strt bit. set- ting strt clears the stop bit. strt is read/write and is set with one only. writing a 0 into this bit has no effect. strt is cleared by reset or by setting the stop bit. 00 init initialize, when set, causes the c-lance to begin the initialization procedure and access the initializa- tion block. the stop bit must be set prior to setting the init bit. setting init clears the stop bit. init is read/write with 1 only. writing a 0 into this bit has no effect. init is cleared by reset or by setting the stop bit. the c-lance latches csr 0 during a slave read; therefore, the csr 0 status bits are guaranteed to be sta- ble for the duration of the csr 0 access. control and status register 1 (csr1) read/write : accessible only when the stop bit of csr 0 is a one and rap = 01. the c-lance preserves the con- tents of csr 1 after stop. 0 15 1 0 iadr (15:01) 17881b-16 bit name description 15:01 iadr the low order 15 bits of the address of the first word (lowest address) in the initialization block. 00 must be zero. control and status register 2 (csr2) read/write: accessible only when the stop bit of csr 0 is a one and rap = 10. the c-lance preserves the con- tents of csr 2 after stop. 15 0 iadr (23:16) 17881b-17 87 res bit name description 15:08 res reserved. read as zeroes. write as zeroes. 07:00 iadr the high order 8 bits of the address of the first word (lowest address) in the initialization block.
p r e l i m i n a r y amd 23 AM79C90 control and status register 3 (csr3) csr3 allows redefinition of the bus master interface. read/write : accessible only when the stop bit of csr 0 is one and rap = 11. csr 3 is cleared by reset or by setting the stop bit in csr 0 . 15 0 2 1 3 bcon acon bswp res 17881b-18 bit name description 15:03 res reserved. read as zeroes. write as zeroes. 02 bswp byte swap allows the chip to oper- ate in systems that consider bits (15:08) of data to be pointed at an even address and bits (07:00) to be pointed at an odd address. when bswp = 1, the c-lance will swap the high and low bytes on dma data transfers between the receive fifo and bus memory. only data from the receive fifo transfers is swapped; the initialization block data and the descriptor ring entries are not swapped. bswp is read/write and cleared b y reset or by setting the stop bit in csr 0 . 01 acon ale control defines the asser- tive state of ale when the c-lance is a bus master. acon is read/ write and cleared by reset and by setting the stop bit in csr 0 . acon ale 0 asserted high 1 asserted low 00 bcon byte control redefines the byte mask and hold l/o pins. bcon is read/write and cleared by reset or by setting the stop bit in csr 0 . bcon pin 16 pin 1 5 pin 17 0 bm 1 bm 0 hold 1 busak o byt e busrq all data transfers from the c-lance in the bus master mode are in words. however, the c-lance can handle odd address boundaries and/or packets with an odd number of bytes. initialization initialization block chip initialization includes the reading of the initializa- tion block in memory to obtain the operating parame- ters. the following is a definition of the initialization block. the initialization block is read by the c-lance when the init bit in csr0 is set. the init bit should be set be- fore or concurrent with the strt bit to insure proper pa- rameter initialization and chip operation. after the c-lance has read the initialization block, idon is set in csr0 and an interrupt is generated if inea = 1. higher address tlenCtdr (23:16) iadr +22 tdra (15:00) iadr +20 rlenCrdra (23:16 ) iadr +18 rdra (15:00) iadr +16 ladrf (63:48) iadr +14 ladrf (47:32) iadr +12 ladrf (31:16) iadr +10 ladrf (15:00) iadr +08 padr (47:32) iadr +06 padr (31:16) iadr +04 padr (15:00) iadr +02 base address of bloc k mode iadr +00 mode the mode register allows alteration of the c-lances operating parameters. normal operation is with the mode register clear. drx dtx loop dtcr coll drty intl 15 0 2 1 3 4 6 5 7 res prom 14 17881b-19 8 emba
amd p r e l i m i n a r y 2 4 AM79C90 bit name description 15 prom promiscuous mode. when prom = 1, all incoming packets are accepted. 14:08 res reserved. read as zeroes. write as zeroes. 07 emba enable modified back-off algorithm. when set (emba=1), enables the modified backoff algorithm. emba is cleared by activation of the reset pin or setting the stop bit. 06 intl internal loopback is used with the loop bit to determine where the loopback is to be done. internal loop- back allows the chip to receive its own transmitted packet. since this represents full duplex operation, the packet size is limited to 8C32 bytes. internal loopback in the c-lance is operational when the packets are addressed to the node itself. the c-lance will not receive any packets externally when it is in inter- nal loopback mode. external loopback allows the c-lance to transmit a packet through the sia transceiver cable out to the ethernet medium. it is used to determine the operability of all circuitry and connections be- tween the c-lance and the physi- cal medium. multicast addressing in external loopback is valid only when dtcr = 1 (user needs to append the 4 bytes crc). in external loopback, the c-lance also receives packets from other nodes. the fifos read/write pointers may misalign in the c-lance under heavy traffic. the packet could then be corrupted or not received. therefore, the external loopback execution may need to be repeated. see specific discussion under loopback in later section. intl is only valid if loop = 1; other- wise, it is ignored. loop intl loopback 0 x no loopback, normal 1 0 external 1 1 internal 05 drty disable retry. when drty = 1, the c-lance will attempt only one transmission of a packet. if there is a collision on the first transmission at- tempt, a retry error (rtry) will be reported in transmit message de- scriptor 3 (tmd 3 ). bit name description 04 coll force collision. this bit allows the collision logic to be tested. the c-lance must be in internal loop- back mode for coll to be valid. if coll = 1, a collision will be forced during the subsequent transmission attempt. this will result in 16 total transmission attempts with a retry er- ror reported in tmd 3 . 03 dtcr disable transmit crc. when dtcr = 0, the transmitter will gener- ate and append a crc to the trans- mitted packet. when dtcr = 1, the crc logic is allocated to the receiver and no crc is generated and sent with the transmitted packet. the add_fcs bit (bit 13, tmd 1 ) can be used to override a dtcr=1 setting on a per packet basis. during loopback, dtcr = 0 will cause a crc to be generated on the transmitted packet, but no crc check will be done by the receiver since the crc logic is shared and cannot generate and check crc at the same time. the generated crc will be written into memory with the data and can be checked by the host software. if dtcr = 1 during loopback, the host software must append a crc value to the transmit data. the receiver will check the crc on the received data and report any errors. 02 loop loopback allows the c-lance to operate in full duplex mode for test purposes. the packet size is limited to 8C32 bytes.the received packet can be up to 36 bytes (32 + 4 bytes crc) when dtcr = 0. during loop- back, the runt packet filter is disabled because the maximum packet is forced to be smaller than the minimum size ethernet packet (6 4 bytes). loop = 1 allows simultaneous transmission and reception for a message constrained to fit within the transmit fifo. the c-lance waits until the entire message is in the transmit fifo before serial trans- mission begins. the incoming data stream fills the receive fifo. mov- ing the received message out of the receive fifo to memory does not begin until reception has ceased.
p r e l i m i n a r y amd 2 5 AM79C90 bit name description in loopback mode, transmit data chaining is not possible. receive data chaining is possible if receive buffers are 32 bytes long to allow time for lookahead. 01 dtx disable the transmitter causes the c-lance to not access the transmitter descriptor ring, and therefore, no transmissions are at- tempted. dtx = 1 will clear the txon bit in csr 0 when initialization is complete. 00 drx disable the receiver causes the c-lance to reject all incoming packets and not access the receive descriptor ring. drx = 1 will clear the rxon bit in the csr 0 when in- itialization is complete. 0 47 1 0 padr (47:01) 17881b-20 47:00 padr physical address is the unique 48-bit physical address assigned to the c-lance. padr (0) must be zero. logical address filter 63 0 17881b-21 ladrf 63:00 ladrf the 64-bit mask used by the c-lance to accept logical addresses. the purpose of logical (or group or multicast) addresses is to allow a group of nodes in a network to receive the same message. each node can maintain a list of multi- cast addresses that it will respond to. the logical ad- dress filter mechanism in the c-lance is a hardware aide that reduces the average amount of host computer time required to determine whether or not an incoming packet with a multicast destination address should be accepted. the logical address filter hardware is an implementation of a hash code searching technique commonly used by software programmers. if the multicast bit of the desti- nation address of an incoming packet is set, the hardware maps this address into one of 64 categories which correspond to 64 bits in the logical address filter register. the hardware then accepts or rejects the packet depending on the state of the bit in the logical address filter register which corresponds to the se- lected category. for example, if the address maps into category 24, and bit 24 of the logical address filter regis- ter is set, the packet is accepted. a node can be made a member of several groups by set- ting the appropriate bits in the logical address filter register. the details of the hardware mapping algorithm are as follows: if the first bit of an incoming address is a 1 [padr (0) =1], the address is deemed logical and is passed through the logical address filter. the logical address filter is a 64-bit mask composed of four sixteen-bit registers, ladrf (63:00) in the initiali- zation block, that is used to accept incoming logical ad- dresses. the incoming address is sent through the crc circuit. after all 48 bits of the address have gone through the crc circuit, the high order 6 bits of the resultant crc (32-bit crc) are strobed into a register. this regis- ter is used to select one of the 64-bit positions in the logical address filter. if the selected filter bit is a 1, the address is accepted and the packet will be put in mem- ory. the logical address filter only assures that there is a possibility that the incoming logical address belongs to the node. to determine if it belongs to the node, the in- coming logical address that is stored in main memory is compared by software to the list of logical addresses to be accepted by this node. the task of mapping a logical address to one of 64-bit positions requires a simple computer program (see ap- pendix a) which uses the same crc algorithm (used in c-lance and defined per ethernet) to calculate the hash (see figure 7). driver software that manages a list of multicast ad- dresses can work as follows. first the multicast address list and the logical address filter must be initialized. some sort of management function such as the driver initialization routine passes to the driver a list of ad- dresses. for each address in the list the driver uses a subroutine similar to the one listed in the appendix to set the appropriate bit in a software copy of the logical ad- dress filter register. when the complete list of addresses has been processed, the register is loaded. later, when a packet is received, the driver first looks at the individual/group bit of the destination address of the packet to find out whether or not this is a multicast ad- dress. if it is, the driver must search the multicast ad- dress list to see if this address is in the list. if it is not in the list, the packet is discarded.
amd p r e l i m i n a r y 2 6 AM79C90 the broadcast address, which consists of all ones is a special multicast address. packets addressed to the broadcast address must be received by all nodes. since broadcast packets are usually more common than other multicast packets, the broadcast address should be the first address in the multicast address list. the broadcast address does not go through the logical address filter and is always enabled. if the logical ad- dress filter is loaded with all zeroes, all incoming logical addresses except broadcast will be rejected. the multi- cast addressing in external loopback is operational only when dtcr in the mode register is set to 1. destination address 47 1 0 crc gen 32-bit resultant crc 31 26 0 logical address filter 63 0 1 enable 64 mux select match* 6 *match - 1, the packet is accepted match - 0, the packet is rejected 17881b-22 figure 7. logical address filter operation receive descriptor ring pointer 31 2 0 17881b-23 2 9 2 8 2 4 23 3 res rlen 000 (quadword boundary) rdra (23:03) bit name description 31:29 rlen receive ring length is the number of entries in the receive ring expressed as a power of two. rlen number of entries 01 12 24 38 4 1 6 5 3 2 6 6 4 7 128 28:24 res reserved. read as zeroes. write as zeroes. 23:03 rdra receive descriptor ring ad- dress is the base address (lowest address) of the receive descriptor ring. 02:00 must be zeroes. these bits are rdra (02:00) and must be zeroes because the receive ring is aligned on a quadword boundary. transmit descriptor ring pointer 31 2 0 17881b-24 2 9 2 8 2 4 23 3 res tlen 000 (quadword boundary) tdra (23:03) 31:29 tlen transmit ring length is the number of entries in the transmit ring expressed as a power of two. tlen number of entries 01 12 24 38 4 1 6 5 3 2 6 6 4 7 128 28:24 res reserved. read as zeroes. write as zeroes. 23:03 tdra transmit descriptor ring address is the base address (low- est address) of the transmit de- scriptor ring. 02:00 must be zeroes. these bits are tdra (02:00) and must be zeroes because the transmit ring is aligned on a quadword boundary.
p r e l i m i n a r y amd 27 AM79C90 buffer management buffer management is accomplished through message descriptors organized in ring structures in memory. each message descriptor entry is four words long. there are two rings allocated for the device: a receive ring and a transmit ring. the device is capable of polling each ring for buffers to either empty or fill with packets to or from the channel. the device is also capable of enter- ing status information in the descriptor entry. c-lance polling is limited to looking one ahead of the descriptor entry the c-lance is currently working with. the location of the descriptor rings and their length are found in the initialization block, accessed during the in- itialization procedure by the c-lance. writing a one into the strt bit of csr0 will cause the c-lance to start accessing the descriptor rings and enable it to send and receive packets. the c-lance communicates with a host device through the ring structures in memory. each entry in the ring is either owned by the c-lance or the host. there is an ownership bit (own) in the message de- scriptor entry. mutual exclusion is accomplished by a protocol which states that each device can only relin- quish ownership of the descriptor entry to the other de- vice; it can never take ownership, and no device can change the state of any field in any entry after it has relin- quished ownership. descriptor ring each descriptor in a ring in memory is a 4-word entry. the following is the format of the receive and the trans- mit descriptors. receive message descriptor entry receive message descriptor 0 (rmd0) 15 0 17881b-25 ladr bit name description 15:00 ladr the low order 16 address bits of the buffer pointed to by this descrip- tor. ladr is written by the host and is not changed by the c-lance. receive message descriptor 1 (rmd1) enp stp buff crc oflo fram err own 15 8 7 0 hadr 17881b-26 bit name description 15 own this bit indicates that the descriptor entry is owned by the host (own = 0) or by the c-lance (own = 1). the c-lance clears the own bit after filling the buffer pointed to by the de- scriptor entry. the host sets the own bit after emptying the buffer. once the c-lance or host has relin- quished ownership of a buffer, it must not change any field in the four words that comprise the descriptor entry. 14 err error summary is the or of fram, oflo, crc or buff. 13 fram framing error indicates that the incoming packet contained a non-integer multiple of eight bits and there was a crc error. if there was not a crc error on the incoming packet, then fram will not be set even if there was a non-integer multi- ple of eight bits in the packet. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not.
amd p r e l i m i n a r y 28 AM79C90 bit name description 12 oflo overflow error indicates that the receiver has lost all or part of the in- coming packet due to an inability to store the packet in a memory buffer before the internal receive fifo overflowed. oflo is valid only when enp is not set. 11 crc crc indicates that the receiver has detected a crc error on the incom- ing packet. crc is valid only when enp is set and oflo is not. 10 buff buffer error is set any time the c-lance does not own the next buffer while data chaining a received packet. this can occur in either of two ways: 1) the own bit of the next buffer is zero, or 2) the receive fifo overflow occurred before the c-lance has performed a lookahead poll of the next receive descriptor. if a buffer error occurs, an overflow error may also occur internally in the receive fifo, but will not be re- ported in the descriptor status entry unless both buff and oflo errors occur at the same time. 09 stp start of packet indicates that this is the first buffer used by the c-lance for this packet. it is used for data chaining buffers. 08 enp end of packet indicates that this is the last buffer used by the c-lance for this packet. it is used for data chaining buffers. if both stp and enp are set, the packet fits into one buffer and there is no data chaining. 07:00 hadr the high order 8 address bits of the buffer pointed to by this descrip- tor. this field is written by the host and unchanged by the c-lance. receive message descriptor 2 (rmd2) 15 0 17881b-27 1 2 11 bcnt must be ones 15:12 must be ones. this field is written by the host and is not changed by the c-lance. 11:00 bcnt buffer byte count is the length of the buffer pointed to by this de- scriptor, expressed as a twos com- plement number. this field is written by the host and is not changed by the c-lance. minimum buffer size is 64 bytes for the first buffer of packet. receive message descriptor 3 (rmd3) 15 0 17881b-28 1 2 11 mcnt res 15:12 res reserved. read as zeroes. write as zeroes. 11:00 mcnt message byte count is the length in bytes of the received mes- sage. mcnt is valid only when err is clear and enp is set. mcnt is writ- ten by the chip and cleared by the host. transmit message descriptor entry transmit message descriptor 0 (tmd0) 15 0 17881b-29 ladr bit name description 15:00 ladr the low order 16 address bits of the buffer pointed to by this descrip- tor. ladr is written by the host and is not changed by the c-lance. transmit message descriptor 1 (tmd1) enp stp def one more add_fcs err own 15 8 7 0 hadr 17881b-30
p r e l i m i n a r y amd 29 AM79C90 bit name description 15 own this bit indicates that the descriptor entry is owned by the host (own = o) or by the c-lance (own = 1). the host sets the own bit after filling the buffer pointed to by this descrip- tor. the c-lance clears the own bit after transmitting the contents of the buffer. neither the host nor the c- lance may alter a descriptor entry after it has relinquished ownership. 14 err error summary is the or of lcol, lcar, uflo or rtry. 13 add_fcs setting add_fcs=1, instructs the controller to append a crc to this transmitted frame, regardless of the setting of the dtcr bit (bit 3 in the mode register). the add_fcs bit allows the controller to be configured to append crc on a per packet ba- sis, when dtcr=1. add_fcs is only valid when stp=1. 12 more more indicates that more than one retry was needed to transmit a packet. 11 one one indicates that exactly one retry was needed to transmit a packet. the one flag is not valid when lcol is set. 10 def deferred indicates that the c-lance had to defer while trying to transmit a packet. this condition oc- curs if the channel is busy when the c-lance is ready to transmit. 09 stp start of packet indicates that this is the first buffer to be used by the c-lance for this packet. it is used for data chaining buffers. stp is set by the host and is not changed by the c-lance. the stp bit must be set in the first buffer of the packet, or the c-lance will skip over this descriptor and poll the next descrip- tor(s) until the own and stp bits ar e set. 08 enp end of packet indicates that this is the last buffer to be used by the c- lance for this packet. it is used for data chaining buffers. if both stp and enp are set, the packet fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the c-lance. 07:00 hadr the high order 8 address bits of the buffer pointed to by this descrip- tor. this field is written by the host and is not changed by the c-lance. transmit message descriptor 2 (tmd2) 15 0 17881b-31 1 2 11 bcnt ones bit name description 15:12 ones must be ones. this field is set by the host and is not changed by the c-lance. 11:00 bcnt buffer byte count is the us- able length in bytes of the buffer pointed to by this descriptor ex- pressed as a negative twos comple- ment number. this is the number of bytes from this buffer that will be transmitted by the c-lance. this field is written by the host and is not changed by the c-lance. the first buffer of a packet has to be at least 100 bytes minimum when data chaining and 64 byte (dtcr = 1) or 60 bytes (dctr = 0) when not data chaining.
amd p r e l i m i n a r y 30 AM79C90 transmit message descriptor 3 (tmd3) rtry lcar lcol res uflo buff 15 1 0 9 0 tdr 17881b-32 bit name description 15 buff buffer error is set by the c-lance during transmission when the c-lance does not find the enp flag in the current buffer and does not own the next buffer. this can oc- cur in either of two ways: either the own bit of the next buffer is zero, or transmit fifo underflow occurred before the c-lance has performed a lookahead poll of the next transmit descriptor. buff is set by the c-lance and cleared by the host. buff error will turn off the transmit- ter (csr 0 , txon = 0). if a buffer error occurs, an underflow error will also occur. buff error is not valid when lcol or rtry error is set during tx data chaining. 14 uflo underflow error indicates that the transmitter has truncated a message due to data late from mem- ory. uflo indicates that the trans- mit fifo has emptied before the end of the packet was reached. upon uflo error, transmitter is turned off (csr 0 , txon = 0). 13 res reserved bit. the c-lance will write this bit with a 0. 12 lcol late collision indicates that a collision has occurred after the slot time of the channel has elapsed. the c-lance does not retry on late collisions. 11 lcar loss of carrier is set when the carrier input (rena) to the c-lance goes false during a c-lance-initiated transmission. the c-lance does not retry upon loss of carrier. it will continue to transmit the whole packet until done. lcar is not valid in internal loopback mode. 10 rtry retry error indicates that the transmitter has failed in 16 attempts to successfully transmit a message due to repeated collisions on the me- dium. if drty = 1 in the mode reg- ister, rtry will set after 1 failed transmission attempt. 09:00 tdr time domain reflectometry reflects the state of an internal c- lance counter that counts from the start of a transmission to the occur- rence of a collision. this value is useful in determining the approxi- mate distance to a cable fault. the tdr value is written by the c-lance and is valid only if rtry i s set. ring access mechanism in the c-lance once the c-lance is initialized through the initializa- tion block and started, the cpu and the c-lance com- municate via transmit and receive rings, for packet transmission and reception. there are 2 sets of ram locations (four 16-bit register per set, corresponding to the 4 entries in each descrip- tor) in the c-lance. the first set points to the current buffer, and they are the working registers which are used for transferring the data for the packet. the second set contains the pointers to the next buffer in the ring which the c-lance obtained from the lookahead operation. there are three types of ring access in the c-lance. the first type is when the c-lance polls the rings to own a buffer. the second type is when the buffers are data chained. the c-lance does a lookahead opera- tion between the time that it is transferring data to/from the transmit/receive fifos; this lookahead is done only once. the third type is when the c-lance tries to own the next descriptor in the ring when it clears the own bit for the current buffer. transmit ring buffer management when there is no ethernet activity, the c-lance will automatically poll the transmit ring in the memory once it has started (csr0, strt = 1). this polling occurs every 1.6 ms, (csr0 tdmd bit = 0) and consists of reading the status word of the transmit descriptor, tmd1, until the c-lance owns the descriptor. the c-lance will read tmd0 and tmd2 to get the rest of the buffer ad- dress and the buffer byte count when it owns the de- scriptor. each of these memory reads is done separately with a new arbitration cycle for each transfer. if the transmit buffers are data chained (current buffer enp = 0), the c-lance will look ahead to the next de- scriptor in the ring while transferring the current buffer into the transmit fifo (see figure 8-1). the c-lance does this lookahead only once. if it does not own the next transmit descriptor table entry (dte) (2nd tx ring
p r e l i m i n a r y amd 31 AM79C90 for this packet) it will transmit the current buffer and up- date the status of current ring with the buff and uflo error bits set. if the c-lance owns the 2nd dte, it will also read the buffer address and the buffer byte count of this entry. once the c-lance has finished emptying the current buffer, it clears the own bit for this buffer, and immediately starts loading the transmit fifo from the next (2nd) buffer. between dma bursts, starting from the 2nd buffer, the c-lance does a lookahead again to check if it owns the next (3rd) buffer. this activity goes on until the last transmit dte indicates the end of the packet (tmd1, enp = 1). once the last part of the pack- et has been transmitted out from the transmit fifo to the medium, the c-lance will update the status in tmd1, tmd3 (tmd3 is updated only when there is an error) and will relinquish the last buffer to the cpu. the c-lance tries to own the next buffer (first buffer of the next packet), immediately after it relinquishes the last buffer of the current packet. this guarantees the back- to-back transmission of the packets. if the c-lance does not own the next buffer, it then polls the tx ring every 1.6 ms. when an error occurs before all of the buffers get trans- mitted, the status, tmd3 , is updated in the current dte, own bit is cleared in tmd1, and tint bit is set in csr0 which causes an interrupt if inea = 1. the c-lance will then skip over the rest of the descriptors for this packet (clears the own bit and sets the tint bit in csr0) until it finds a buffer with both the stp and own bit being set (this indicates the first buffer for the next packet). when the transmit buffers are not data chained (current descriptors enp = 1), the c-lance will not perform any lookahead operation. it will transmit the current buffer, update the tmd3 if any error, and then update the status and clear the own bit in tmd1 . the c-lance will then immediately check the next descriptor in the ring to see if it owns it. if it does, the c-lance will also read the rest of the entries from the descriptor table. if the c-lance does not own it, it will poll the ring once every 1.6 ms until it owns it. user may set the tdmd bit in csr0 when it has relinquished a buffer to the c-lance. this will force the c-lance to check the own bit at this buffer without waiting for the polling time to elapse. receive ring buffer management receive ring access is similar to the transmit ring ac- cess. once the receiver is enabled, the c-lance will al- ways try to have a receive buffer available, should there be a packet addressed to this node for reception. there- fore, when the c-lance is idle, it will poll the receive ring entry once every 1.6 ms, until it owns the current re- ceive dte. once the c-lance owns the buffer, it will read rmd0 and rmd2 to get the rest of buffer address and buffer byte count. when a packet arrives from the physical medium, after the address recognition logic accepts the packet, the c-lance will immediately poll the receiver ring once for a buffer. if it still does not own the buffer, it will set the miss error in csr0 and will not poll the receive ring until the packet ends. assuming the c-lance owns a receive buffer when the packet arrives, it will perform a lookahead operation on the next dte between periods when it is dumping the re- ceived data from the receive fifo to the first receive buffer in case the current buffer requires data chaining. when the c-lance owns the buffer, the lookahead op- eration consists of three separate single word dma reads: rmd1, rmd0, and rmd2. when the c-lance does not own the next buffer, the lookahead operation consists of only one single dma read, rmd1. either lookahead operation is done only once. following the lookahead operation, whether c-lance owns the next buffer or not, the c-lance will transfer the data from receive fifo to the first receive buffer for this packet in burst mode (8 word transfer per one dma cycle arbitration). if the packet being received requires data chaining, and the c-lance does not own the second dte, the c-lance will update the current buffer status, rmd1, with the buff and/or oflo error bits set. if the c-lance does own the next buffer (second dte) from previous lookahead, the c-lance will relinquish the current buffer and start filling up the second buffer for this packet. between the time that the c-lance is transferring data from the receive fifo to the second buffer, it does a lookahead operation again to see if it owns the next (third) buffer. if the c-lance does own the third dte, it will also read rmd0, and rmd2 to get the rest of buffer pointer address and buffer byte count. this activity continues on until the c-lance recognizes the end of the packet (physical medium is idle); it then updates the current buffer status with the end of packet bit (enp) set. the c-lance will also update the mes- sage byte count (rmd3) with the total number of bytes received for this packet in the current buffer (the last buffer for this packet). the dual fifos in the c-lance are utilized by the inter- nal microcode to guarantee that continuous receive ac- tivity does not prevent the servicing of pending transmit packets. the microcode includes a single transmit de- scriptor poll operation at the beginning of buffer dma operations for an incoming receive packet. this single transmit descriptor poll is performed only once during the receive microcode routine for each packet that is re- ceived. if the own bit in the transmit descriptor is set, burst transfers to the transmit fifo are interleaved with burst transfers from the receive fifo. by interleaving the transmit buffer transfers with the receive buffer transfers, the beginning of the transmit packet is preloaded in the transmit fifo, ready to be transmitted immediately following the end of the receive packet on the wire.
amd p r e l i m i n a r y 32 AM79C90 17881b-33 12 3 4 5 6 7 0 127 output packet c a b a b c figure 8-1. data chaining (transmit) notes: 1. w, x, y, z are the packets queued for transmission. 2. a, b, c, d are the packets received by the c-lance. 17881b-34 12 3 4 5 6 7 0 127 c-lance cpu w xy z (note 1) c-lance 127 0 1 2 3 4 5 a bc d (note 2) cpu transmit receive figure 8-2. buffer management descriptor rings c-lance dma transfer (bus master mode) there are two types of dma transfers with the c-lance: burst mode dma single word dma burst mode dma burst dma is used for transmission or reception of the packets, (read/write from/to memory). the burst transfers are 8 consecutive word reads (transmit) or writes (receive) that are done in a single bus arbitration cycle. in other words, once the c-lance receives the bus acknowledge, ( hlda = low), it will do 8 word transfers (8 dma cycle, min. at 600 ns per cycle) without releasing the bus request signal ( hold = low). if there are more than 16 bytes empty in the transmit fifo, in transmit mode, or at least 16 bytes of data, in the receive fifo in receive mode, when the c-lance releases the bus ( hold deasserted), the c-lance will request the bus again within 700 ns ( hold dwell time). burst dmas are always 8 transfer cycles unless there are fewer than 8 words left to be transferred to/from the transmit/receive fifo, or if there are fewer than 8 words left to be transferred to/ from the rx/tx buffer. transmit dmas may be shorter than 8 words if a collision is detected during the dma. single word dma transfer the c-lance initiates single word dma transfers to ac- cess the transmit and receive rings or the initialization block. the c-lance will not initiate any burst dma transfers while reading the initialization block. the c-lance will not initiate any burst dma transfers be- tween the time that it discovers ownership of a descrip- tor and the time that it reads the buffer pointer and buffer byte count entries of that descriptor. fifo operation the dual fifos provide temporary buffer storage for data being transferred between the parallel bus l/o pins and serial i/o pins. the capacity of the transmit fifo is 48 bytes and the receive fifo is 64 bytes. transmit data is loaded into the transmit fifo under internal microprogram control. the transmit fifo has to have more than 16 bytes empty before the c-lance re- quests the bus ( hold is asserted). the c-lance will start sending the preamble (if the line is idle) as soon as the first byte is loaded to the transmit fifo from memory. receive data is loaded into the receive fifo from the serial in- put shift register during reception. data leaves the re- ceive fifo under microprogram control. the c-lance microcode will wait until there are at least 16 bytes of data in the receive fifo before initiating a dma burst transfer. preamble and start frame delimiter (sfd) are not loaded into the receive fifo. fifos C memory byte alignment memory buffers may begin and end on arbitrary byte boundaries. parallel data is byte aligned between the transmit or receive fifo and dal lines (dal0Cdal15). byte alignment can be reversed by set- ting the byte swap (bswp) bit in csr3. transmission C word read from even mem- ory address bswp=0: fifo byte n get s dal <07:00> fifo byte n + 1 gets dal <15:08> bswp=1: fifo byte n gets da l <15:08> fifo byte n + 1 get s da l <07:00> transmission C byte read from even memory address
p r e l i m i n a r y amd 33 AM79C90 bswp=0: fifo byte n gets da l <07:00> Cdont care gets da l <15:08> bswp=1: fifo byte n gets da l <15:08> Cdont care gets da l <07:00> transmission C byte read from odd memory address bswp=0: fifo byte n gets da l <15:08> Cdont car e gets da l <07:00> bswp=1: fifo byte n gets da l <07:00> Cdont care gets da l <15:08> reception C word write to even memory address bswp=0: da l <07:00> gets fifo byte n da l <15:08> gets fifo byte n + 1 bswp=1: da l <15:08> gets fifo byte n da l <07:00> gets fifo byte n + 1 reception C byte write to even memory address bswp=0: da l <07:00> gets fifo byte n dal <15:08> Cundefined bswp=1: da l <15:08> gets fifo byte n dal <07:00> Cundefined reception C byte write to odd memory address bswp=0: da l <07:00 > Cundefined da l <15:08> gets fifo byte n bswp=1: da l <15:08> Cundefined da l <07:00> gets fifo byte n the c-lance recovery and reinitialization the transmitter and receiver section of the c-lance are turned on via the initialization block (mode reg: drx, dtx bits). the state of the transmitter and the re- ceiver are monitored through the csr0 register (rxon, txon bits). the c-lance must be reinitialized if the transmitter and/or the receiver has not been turned on during the original initialization, and later it is desired to have them turned on. when either the transmitter or re- ceiver shuts off because an error (merr, uflo, tx buff error), it is necessary to reinitialize the c-lance to turn the transmitter and/or receiver back on again. the user should rearrange the descriptors in the trans- mit or receive ring prior to reinitialization. this is neces- sary since the transmit and receive descriptor pointers are reset to the beginning of the ring upon initialization. to reinitialize the c-lance, the user must first stop the c-lance by setting the stop bit in csr0. the user needs to reprogram csr3 because its contents get cleared when the stop bit gets set (csr3 reprogram- ming is not needed when default values of bcon, acon, and bswp are used; bcon, acon, and bswp default values are 0, 0, and 0 respectively). only then the user may set the init bit in csr0. it is recommended that the c-lance not be re-started, once it has been stopped (stop = 1 in csr0), by set- ting the strt bit in csr0 without reinitialization. re- starting the c-lance in this way puts the c-lance in operation in accordance with the parameters set up in the mode register, but the contents of the descriptor pointers in the c-lance will not be guaranteed. frame formatting the c-lance performs the encapsulation/decapsula- tion function of the data link layer (second layer of iso model) as follows: transmlt in transmit mode, the user must supply the destination address, source address, and type field (or length field) as a part of data in transmit data buffer memory. the c-lance will append the preamble, sfd, and crc (fcs) to the frame as is shown in figures 9-1 an d 9-2. receive in receive mode, the c-lance strips off the preamble and sfd and transfers the rest of the frame, including the crc bytes (4 bytes), to the memory. the c-lance will discard packets with less than 64 bytes (runt packet) and will reuse the receive buffer for the next packet. this is the only case where the packet is discarded after the packet has been transferred to the receive buffer. a runt packet is normally the result of a collision. preamble 1010 ... 1010 synch 11 dest. adr source adr type data fcs 62 bits 2 bits 6 bytes 6 bytes 2 bytes 46C1500 bytes 4 bytes 17881b-35 figure 9-1. ethernet frame format llc data preamble 1010 ... 1010 sfd 10101011 dest. adr source adr length fcs 56 bits 8 bits 6 bytes 6 bytes 2 bytes 46C1500 bytes 4 bytes 17881b-36 pad figure 9-2. ieee 802.3 mac frame format framing error (dribbling bits) the c-lance can handle up to 7 dribbling bits when a received packet terminates; the input to the c-lance, rclk, stops following the deassertion of rena. during the reception, the crc is generated on every serial bit (including the dribbling bits) coming from the medium,
amd p r e l i m i n a r y 34 AM79C90 and the crc gets sampled internally on every byte boundary. the framing error is reported to the user as follows: if the number of the dribbling bits is 1 to 7 bits and there is no crc error, then there is no framing error (fram = 0). if the number of the dribbling bits is less than 8 and there is a crc error, then there is also a framing error (fram = 1). if the number of the dribbling bits = 0, then there is no framing error. there may or may not be a crc error. interframe spacing (ifs) the c-lance implements the two-part deferral algo- rithm following both receive and transmit activity, as specified as an option in the ieee 802.3 standard (iso/ iec 8802-3 1990). with two-part deferral, the interframe spacing, which begins immediately after the negation of rena, is divided into two parts, ifs1 and ifs2. if rena is asserted during ifs1, the interframe spacing counter is continually reset until rena is deasserted (any pend- ing transmissions will defer to the incoming receive traf- fic and the incoming frame may be received by the c-lance). once the interframe spacing counter reaches ifs2, the counter proceeds, regardless of the state of rena. when ifs2 expires, the c-lance may begin transmitting a frame if there is one pending. in the c-lance, ifs1 is 6.0 m s and ifs2 is 3.6 m s, mak- ing the minimum possible interframe spacing 9.6 m s. the 9. 6 m s minimum interframe spacing complies with ieee 802.3 specifications. following each frame transmission, the c-lance blinds itself from any receive activity for the first 4.1 m s of the interframe spacing. the c-lance begins looking for the 011 start frame delimiter pattern after 800ns (8 bit times) of preamble has passed. hence, if rena is as- serted during the first 4.1 m s of the interframe spacing, there must be at least 8 bits of preamble left following the end of the 4.1 m s window in order for the frame to be received correctly. following each frame reception, the c-lance blinds it- self from any receive activity for the first 0.5 m s of the in- terframe spacing. collision detection and collision jam collisions are detected by monitoring the clsn pin. if clsn becomes asserted during a frame transmission, tena will remain asserted for at least 32 (but not more than 40) additional bit times (including clsn synchroni- zation). this additional transmission after collision is referred to as collision jam. if collision occurs during the transmission of the preamble, the c-lance continues to send the preamble, and sends the jam pat- tern following the preamble. if collision occurs after the preamble, the c-lance will send the jam pattern fol- lowing the transmission of the current byte. the jam pattern is any pattern except the crc bytes. receive based collision if clsn becomes asserted during the reception of a packet, this reception is immediately terminated. de- pending on the timing of collision detection, one of the following will occur. a collision that occurs within 6 byte times of the detection of the sfd (4.8 m s) will result in the packet being rejected because of an address mis- match; the receive fifo write pointer will be reset. a collision that occurs within 64 byte times (51.2 m s) will result in the packet being rejected since it is a runt pack- et. a collision that occurs after 64 byte times (late colli- sion) will result in a truncated packet being written to the memory buffer with the crc error bit most likely being set in the status word of the receive ring. late collision error is not reported in receive mode. transmit based collision when a transmission attempt has been terminated due to the assertion of clsn, (a collision that occurs within 64 byte times), the c-lance will attempt to retry trans- mission 15 more times. the scheduling of the retransmissions is determined by a controlled random- ized process called truncated binary exponential back- off. upon the negation of the collision jam interval, the c-lance calculates a delay before retransmitting. the delay is an integral multiple of the slot time. the slot time is 512 bit times. the number of slot times to delay before the nth retransmission is chosen as a uniformly distributed random integer in the range: 0 r 2 k where k = min (n, 10). when the modified backoff algorithm is enabled (emba), the backoff time may be longer than the mini- mum time specified above. specifically, the backoff count will be suspended whenever a carrier is detected on the network. the backoff count will resume when the carrier drops. this behavior has the effect of making the backoff interval equal to the sum of an integral number of slot times plus the total duration of the carrier on the network during the backoff interval. if all 16 attempts fail, the c-lance sets the rtry bit in the current transmit message descriptor 3, tmd3, in memory, gives up ownership (sets the own bit to zero) for this packet, and processes the next packet in trans- mit ring for transmission. if there is a late collision (colli- sion occurring after 64 byte times), the c-lance will not attempt to transmit this packet again; it will terminate the transmission, note the lcol error in tmd3, and trans- mit the next packet in the ring.
p r e l i m i n a r y amd 3 5 AM79C90 collisionmicrocode interaction the microprogram uses the time provided by colli- sion jam, interpacket delay, and the backoff interval to restore the address and byte counts internally and starts loading the transmit fifo in anticipation of retransmission. it is important that c-lance be ready to transmit when the backoff interval elapses to utilize the channel properly. if, during the backoff interval, rena and clsn are never asserted (no wire activity), the c-lance does not re-poll the own bit and does not re-read the buffer ad- dress and byte count in the transmit descriptor before reloading the transmit data and retransmitting the trans- mit packet. however, if rena or clsn are asserted during the backoff interval, the c-lance must re-poll the own bit and re-read the buffer address and byte count in the transmit descriptor before starting the dma access of the transmit buffer and performing the retry. note that the re-polling of the transmit descriptor could be preceeded by receive dma operations if an incoming packet arrives during the backoff interval and an ad- dress match is detected or when the c-lance is in pro- miscuous mode. time domain reflectometry the c-lance contains a time domain reflectometry counter. the tdr counter is ten bits wide. it counts at a 10 mhz rate. it is cleared by the microprogram and counts upon the assertion of rena during transmission. counting ceases if clsn becomes true, or rena goes inactive. the counter does not wrap around. once all ones are reached in the counter, the counter value is held until cleared. the value in the tdr is written into memory following the transmission of the packet. tdr is used to determine the location of suspected cable faults. heartbeat during the interpacket gap time following the negation of tena, the clsn input is asserted by some transceivers as a self-test. if the clsn input is not asserted within 4 m s following the completion of transmission, then the c-lance will set the cerr bit in csr0. cerr error will not cause an interrupt to occur (intr = 0). cyclic redundancy check (crc) the c-lance utilizes the 32-bit crc function as de- scribed in the ieee 802.3 standard section 3.2.8 to gen- erate the frame check sequence (fcs) field. the c-lance requirements for the crc logic are the following: transmission C mode <02> loop = 0, mode <03> dtcr = 0. the c-lance calculates the crc from the first bit following the sfd to the last bit of the data field. the crc value inverted is ap- pended onto the transmission in one unbroken bit stream. reception C mode <02> loop = 0. the c-lance performs a check on the input bit stream from the first bit following the sfd to the last bit in the frame. the c-lance continually samples the state of the crc check on framed byte bounda- ries, and, when the incoming bit stream stops, the last sample determines the state of the crc error. framing error (fram) is not reported if there is no crc error. loopback C mode <02> loop =1, mode <03> dtrc = 0. the c-lance generates and appends the crc value to the outgoing bit stream as in transmission but does not perform the crc check of the incoming bit stream. loopback C mode <02> loop = 1 mode <03> dtrc = 1. c-lance performs the crc check on the incoming bit stream as in reception, but does not generate or append the crc value to the outgoing bit stream during transmission. loopback the normal operation of the c-lance is as a half- duplex device. however, to provide an on-line opera- tional test of the c-lance, a pseudo-full duplex mode is provided. in this mode simultaneous transmission and reception of a loopback packet are enabled with the fol- lowing constraints: the packet length must be no longer than 3 2 bytes, and no shorter than 8 bytes, exclusive of the crc. serial transmission does not begin until the trans- mit fifo contains the entire output packet. moving the input packet from the receive fifo to the memory does not begin until the serial input bit stream terminates. crc may be generated and appended to the out- put serial bit stream or may be checked on the in- put serial bit stream. crc may not be used for both transmission and reception simultaneously. in internal loopback, the packets should be ad- dressed to the node itself. in external loopback, multicast addressing can be used only when dtcr = 1 is in the mode register. in this case, the user needs to append the crc bytes. loopback is controlled by bits <06, 03, 02> intl, dtcr, and loop of the mode register.
amd p r e l i m i n a r y 36 AM79C90 serial transmission serial transmission consists of sending an unbroken bit stream from the tx output pin consisting of: preamble/sfd: 56 alternating ones and zeroes terminating with the sfd byte (10101011). data: the serialized bit stream from the transmit fifo shifted out with lsb first. crc: the inverted 32-bit polynomial calculated from the data, address, and type field. crc is not transmitted if: transmission of the data field is truncated for any reason. clsn becomes asserted any time during transmission. mode <03> dtcr = 1 in a normal or loopback transmission mode, and add_fcs=0 in the transmit descriptor. the transmission is indicated at the output pin by the assertion of tena with the first bit of the preamble and the negation of tena after the last transmitted bit. the c-lance starts transmitting the preamble when the following are satisfied: there is at least one byte of data to be transmitted in the transmit fifo. the interpacket delay has elapsed. the backoff interval has elapsed, if doing a retransmission. serial reception serial reception consists of receiving an unbroken bit stream on the rx input pin consisting of: preamble/sfd: two ones occurring a minimum of 8 bit times after the assertion of rena. destination address: the 48 bits (6 bytes) follow- ing the sfd. data: the serial bit stream following the destina- tion address. the last 4 complete bytes of data are the crc. the destination address and the data are framed into bytes and enter the receive fifo. source address and length field are part of the data which are transparent to the c-lance. reception is indicated at the input pin by the assertion of rena and the presence of clock on rclk while tena is inactive. the c-lance does not sample the received data until about 800 ns after rena goes high.
p r e l i m i n a r y amd 37 AM79C90 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C25 c to +125 c . . . . . . . . . . . . . . . . . supply voltages to ground potential continuous C0.3 v to +6 v . . . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices temperature (t a ) 0 c to +70 c . . . . . . . . . . . . . . . . . supply voltage (v dd ) +4.75 v to +5.25 v . . . . . . . . . . v ss 0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over operating ranges unless otherwise specified parameter symbol paramete r description tes t conditions min typ max unit v il input low voltag e 0.8 v v ih input high voltag e 2 v v ol output low voltage i ol = 3.2 ma 0.5 v v oh output high voltage i oh = C0.4 ma 2.4 v i il input leakage v in = 0.4 v to v cc 10 m a i dd * power supply current 50 ma commercial *i dd is measured while running a functional pattern with spec. value i oh and i ol load applied. capacitance** (t a = 25 c; v dd = 0) parameter symbol paramete r description tes t conditions min typ max unit c in input pin capacitance f = 1 mhz 10 pf c out output pin capacitance f = 1 mhz 15 pf c io i/o pin capacitance f = 1 mhz 20 pf **parameters are not tested.
amd p r e l i m i n a r y 38 AM79C90 switching characteristics parameter test no. symbol paramete r description conditions min typ max unit 1 t tct tclk period 99 101 ns 2 t tcl tclk low time 45 55 ns 3 t tch tclk high time 45 55 ns 4 t tcr rise time of tclk (note 3) 8 ns 5 t tcf fall time of tclk (note 3) 8 ns 6 t tep tena propagation delay after the 60 ns rising edge of tclk 7 t teh tena hold time after the rising 5 n s edge of tclk 8 t tdp tx data propagation delay after the 60 ns rising edge of tclk 9 t tdh tx data hold time after the rising 5 n s edge of tclk 10 t rct rclk period (note 3) 85 118 ns 11 t rch rclk high time (note 2) 38 ns 12 t rcl rclk low time (note 2) 38 ns 13 t rcr rise time of rclk (note 3) 8 ns 14 t rcf fall time of rclk (note 3) 8 ns 15 t rdr rx data rise time (note 3) 8 ns 16 t rdf rx data fall time (note 3) 8 ns 17 t rdh rx data hold time (rclk to rx (note 2) 5 n s data change) 18 t rds rx data setup time (rx data stable (note 2) 35 ns to the rising edge of rclk) 19 t dpl rena low time 1t tct + 20 ns 20 t cph clsn high time 80 ns 21 t doff bus master driver disable after rising 50 ns edge of hold 22 t don bus master driver enable after falling 50 2t tct + 50 ns edge of hlda 23 t hha delay to falling edge of hlda fro m 0 ns falling edge of hold (bus master) 24 t rw reset pulse width low (note 7) 2t tct ns 25 t cycle read/write, address/data cycle time (note 1) 6t tct ns 26 t xas address setup time to the falling 75 ns edge of ale 27 t xah address hold time after the risin g 35 ns edge of das 28 t as address setup time to the fallin g 75 ns edge of ale 29 t ah address hold time after the fallin g 35 ns edge of ale 30 t rdas data setup time to the rising edg e 40 ns of das (bus master read)
p r e l i m i n a r y amd 39 AM79C90 switching characteristics (continued) parameter test no. symbol paramete r description conditions min typ max unit 31 t rdah data hold time after the rising edge 0 ns of das (bus master read) 32 t ddas data setup time to the falling edge 10 ns o f das (bus master write) 33 t wds data setup time to the rising edge 200 ns o f das (bus master write) 34 t wdh data hold time after the rising edge 35 ns of das (bus master write) 35 t sd01 data driver delay after the falling (csr0 , csr3 , rap) 4t tct ns edge of das (bus slave read) (note 6) 36 t sd02 data driver delay after the falling (csr1, 2) 12t tct ns edge of das (bus slave read) (note 6) 37 t srdh data hold time after the rising 0 5 5 ns edge of das (bus slave read) 38 t swdh data hold time after the rising 0 ns edge of das (bus slave write) 39 t swds data setup time to the falling edge 0 ns o f das (bus slave write) 40 t alew ale width high 120 ns 41 t dale delay from rising edge of das to the 70 ns rising edge of ale 42 t dsw das width low 200 ns 43 t adas delay from the falling edge of ale 80 130 ns to the falling edge of das 44 t ridf delay from the rising of dalo to the 15 ns falling edge of das (bus master read) 45 t rdys delay from the falling edge of ready 65 250 ns to the rising edge of das 46 t roif delay from the rising edge of dalo to 15 ns the falling edge of dali (bus master read) 47 t ris dali setup time to the rising edge of 135 ns das (bus master) 48 t rih dali hold time after the rising edge of 0 ns das (bus master read) 49 t riof delay from the rising edge of dali to the 55 ns falling edge of dalo (bus master read) 50 t os dalo and read setup time to the fallin g 110 ns edge of ale (bus master write and read) 51 t roh dalo hold time after the falling edge o f 35 ns ale (bus master read) 52 t wdsi delay from the rising edge of das to the 35 ns rising edge of dalo (bus master write) 53 t csh cs hold time after the rising edge of das 0 n s (bus slave) 54 t css cs setup time to the falling edge of das 0 n s (bus slave)
amd p r e l i m i n a r y 40 AM79C90 switching characteristics (continued) parameter test no. symbol paramete r description conditions min typ max unit 55 t sah adr hold time after the rising edge of das (bus slave) 0 ns 56 t sas adr setup time to the falling edge of das (bus slave) 0 ns 57 t aryd delay from the falling edge of ale to the 80 ns falling edge of ready to insure a minimum bus cycle time (600 ns) (note 5) 58 t srds data setup time to the falling edge of ready (bus slave read) 75 ns 59 t rdyh ready hold time after the rising edge of das (bus master) 0 ns 60 t sr01 ready driver turn on after the falling (csr0 , csr3 , rap) 6t tct ns edge of das (bus slave) (notes 4, 6) 61 t sr02 ready driver turn on after the fallin g (csr1, 2) 14t tct ns edge of das (bus slave) (note 6) 62 t sryh ready hold time after the rising edge of das (bus slave) 0 3 5 ns 63 t srh read hold time after the rising edge of das (bus slave) 0 ns 64 t srs read setup time to the falling edge of das (bus slave) 0 ns 65 t chl tclk rising edge to hold low or high 95 ns delay 66 t cav tclk to address valid 100 ns 67 t cca tclk rising edge to control signals active 75 ns 68 t cale tclk falling edge to ale low 90 ns 69 t cdl tclk falling edge to das falling edge 90 ns 70 t rcs ready setup time to tclk falling edge (note 5) 0 ns 71 t cdh tclk rising edge to das high 90 ns 72 t hcs hlda setup to tclk falling edge 0 ns 73 t renh rena hold time after the rising edge of 0 ns rclk 74 t csr cs recovery time between deassertion t tct +60 ns of cs or hold and assertion of cs notes: 1. not shown in the timing diagrams, specifies the minimum bus cycle for a single dma data transfer. tested by functional data pattern. 2. applicable parameters associated with receive circuit are tested at t rct (rclk period) = 100 ns, t tct = 100 ns (tclk period). 3. not tested. 4. csr0 write access time (t sr01 ) when stop bit is being set can be as long as 12t tct . 5. it is guaranteed that no wait states will be added by the c-lance if either parameter #57 or #70 is met. 6. parameter is for design reference only. 7. reset must be asserted for at least two rising and two falling edges of tclk for the device to be reset. if reset is deasserted before tclk starts, the device behavior is undefined.
p r e l i m i n a r y amd 4 1 AM79C90 b. open-drain outputs ( intr , hold / busrq , ready ) 100 pf 1.5 v 17881b-37 i ol i oh 100 pf 1.5 v i ol a. normal and three-state outputs 17881b-38
amd p r e l i m i n a r y 42 AM79C90 key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010 switching waveforms (note 1) serial link timing (collision) 17881b-39 clsn 20 rclk rx rena 17881b-40 10 18 16 13 14 12 11 15 17 73 19 serial link timing (receive)
p r e l i m i n a r y amd 43 AM79C90 switching waveforms tclk tx tena rena 4 5 17881b-41 *during transmit, rena input must be asserted (high) and remain active-high before tena goes inactive (low). if rena is deasserted before tena is deasserted, lcar will be reported in tmd 3 after the transmission is completed by the c-lance. 8 9 2 3 1 7 * 6 serial link timing (transmit) drivers enabled o.d. 23 22 24 21 hold hlda bus master drivers reset note: 1 . reset is an asynchronous input to the c-lance and is not part of the bus acquisition timing. when reset is asserted, the c-lance becomes a bus slave. 17881b-42 bus acquisition timing
amd p r e l i m i n a r y 44 AM79C90 switching waveforms dal0Cdal15 das read ready (output from c-lance) hold cs adr read data 74 54 56 55 53 62 37 63 58 o.d see note 1 note: 1. there are two types of delays which depend on which internal register is accessed. type 1 refers to access of csr0 csr3 and rap. type 2 refers to access of csr1 and csr2 which are longer than type 1 delay. 17881b-45 3 6 64 35 60 61 bus slave read timing
p r e l i m i n a r y amd 45 AM79C90 switching waveforms dal0Cdal15 das read ready (output from c-lance) hold cs adr 74 55 o.d 39 64 60 61 38 63 62 54 53 56 17881b-46 write data bus slave write timing
amd p r e l i m i n a r y 4 6 AM79C90 switching waveforms tclk hold hlda a16?23 bm 0, bm 1 ale das ready dal0?al15 (read) dalo (read) dali (read) read (read) 0 100 200 400 500 600 100 200 300 400 500 600 t1 t3 t2 t4 t6 t5 t1 t2 t3 t4 t5 t6 t wait address, bm 0, bm 1 address, bm 0, bm 1 address data in address data in t wait 70 30 45 47 48 49 59 40 41 27 26 68 50 51 29 28 44 46 69 70 43 57 47 48 30 31 59 45 42 71 27 65 21 1st dma 8th dma bus master read timing (burst dma) o.d. 65 67 68 23 66 72 22 26 40 50 28 31 t0 17881b-43 300 700 29
p r e l i m i n a r y amd 4 7 AM79C90 switching waveforms tclk hold hlda a16?23 bm 0, bm 1 ale das ready dal0?al15 (write) dalo (write) dali (write) read (write) 0 100 200 400 500 600 100 200 300 400 500 600 t1 t3 t2 t4 t6 t5 t1 t2 t3 t4 t5 t6 t wait address, bm 0, bm 1 address, bm 0, bm 1 address data out address data out t wait 65 68 66 67 72 26 40 50 70 33 45 34 59 40 41 27 26 68 29 28 69 70 43 57 32 59 45 42 71 65 21 1st dma 8th dma bus master write timing (burst dma) 33 52 o.d. 28 29 t0 23 22 17881b-44 300 700
48 AM79C90 hash filter generation programs for logical addressing appendix a 80x86 computer program example to generate the hash filter, for multicast addressing in the c-lance. 6 ; subroutine to set a bit in the hash filter from a 7 ; given ethernet logical address 8 ; on entry sl points to the logical address with lsb first 9 ; dl points to the hash filter with lsb first 10 ; on return sl points to the byte after the logical address 11 ; all other registers are unmodified 12 ; 13 public sethash 14 assume cs:cse61 15 ; 16 = 1db6 polyl eou 1db6h ;crc polynominal terms 17 = 04c1 polyh equ 04c1h 18 ; 19 0000 cse61 segment public code 20 ; 21 0000 sethas h proc near 22 000 0 50 push ax ;save all registers 23 000 1 53 push bx 24 000 2 51 push cx 25 000 3 52 push dx 26 000 4 55 push bp 27 ; 28 0005 b8 ffff mov ax,0ffffh ;ax,d x =cr c accumulator 29 0008 ba ffff mov dx,0ffffh ;preset crc accumulator to all 1s 30 000 b b 5 03 mov ch,3 ;ch =word counter 31 ; 32 000d 8b 2c seth10: mov bp,[s1] ;get a word of address 33 000f 83 c6 02 add s1,2 ;poin t t o nex t address 34 0012 b1 10 mov cl,16 ;cl=bi t counter 35 ; 36 0014 8b da seth20: mov bx,dx ;get high word of crc 37 0016 d1 c3 rol bx,1 ;put crc31 to lsb 38 001 8 3 3 dd xor bx,bp ;combine crc31 with incomin g bit 39 001a d1 e0 sal ax,1 ;left shift crc accumulator 40 001c d1 d2 rcl dx,1 41 001e 81 e3 0001 and bx,0001h ;bx=control bit 42 002 2 7 4 07 jz seth30 ;do not xor if control bit = 0 43 ; 44 ; perform xor operation when control bit= 1
amd 49 AM79C90 45 ; 46 0024 35 1d 86 xor ax,polyl 47 0027 81 f2 04c1 xor dx,polyh 48 ; 49 002b 0b c3 seth30: or ax,bx ;put control bit in crc0 50 002d d1 cd ror bp,1 ;rotate address word 51 002f fe c9 dec cl ;decremen t bi t counter 52 0031 75 e1 jnz seth20 53 0033 fe cd dec ch ;decremen t wor d counter 54 0035 75 d6 jnz seth10 55 ; formation of crc complete, al contains the reversed hash 56 ; code 58 0037 b9 000a mov cx,10 49 003a d0 e0 seth40: sal al,1 ;reverse the order of bits in al 60 003c d0 dc rcr ah,1 ;and put it in ah 61 003e e2 fa loop seth40 62 63 ; ah now contains the hash code 64 ; 65 0040 8a dc mov bl,a h ;bl = hash code, bh is already zero 66 004 2 b 1 03 mo v cl, 3 ;divide hash code by 8 67 0044 d2 eb sh r bl,c l ;to get to the correct byte 68 0046 b0 01 mov al,01h ;prese t filte r bit 69 0048 80 e45 07 and ah,7h ;extrac t bi t count 70 004b 8a cc mov cl,ah 71 004d d2 e0 shl al,cl ;shift bit to correct position 72 004 f 0 8 01 or [dl + bx],al ;set in hash filter 73 0051 5d pop bp 74 0052 5a pop dx 75 0053 59 pop cx 76 0054 5b pop bx 77 0055 58 pop ax 78 0056 c3 ret 79 ; 80 0057 sethas h endp 81 ; 82 0057 cseg1 ends 83 ; 84 end program example in basic to generate the hash filter, for multicast addressing, in the c-lance. 100 rem 110 rem program to generate a hash number given an ethernet address 120 rem 130 defint aCz 140 dim a(47): rem ethernet address. 48 bits. 150 dim a$(6): rem input from keyboard 160 dim c(32): rem crc registerC32 bits
amd 50 AM79C90 170 print enter ethernet address as 6 hexadecimal numbers separated 180 print by blanks. each number represents one byte. the least 190 print significant bit of the first byte is the first bit transmitted. 200 print 210 print enter ethernet address; 220 input a$(0), a$(1), a$(2), a$(3), a$(4), a$(5) 240 rem 250 rem unpack ethernet address into address array 260 rem 270 m=0 280 for i = 0 to 47: a(i) = 0: next i 290 for i = 0 to 5 300 if len(a$(i)) = 1 then a$(i) = 0 + a$(i) 310 a$(i) = ucase$(a$(i)) 320 for n = 2 to 1 step C1 330 y$ = mid$(a$(i), n, 1) 340 if y$ = 0 then 510 350 if y$ = 1 then a(m) = 1: goto 510 360 if y$ = 2 then a(m + 1) = 1: goto 510 370 if y$ = 3 then a(m + 1) = 1: a(m) = 1: goto 510 380 if y$ = 4 then a(m + 2) = 1: goto 510 390 if y$ = 5 then a(m + 2) = 1: a(m) = 1: goto 510 400 if y$ = 6 then a(m + 2) = 1: a(m + 1) = 1: goto 510 410 if y$ = 7 then a(m + 2) = 1: a(m + 1) = 1: a(m) = 1: goto 510 420 a(m + 3) = 1 430 if y$ = 8 then 510 440 if y$ = 9 then a(m) = 1: goto 510 450 if y$ = a then a(m + 1) = 1: goto 510 460 if y$ = b then a(m + 1) = 1: a(m) = 1: goto 510 470 if y$ = c then a(m + 2) = 1: goto 510 480 if y$ = d then a(m + 2) = 1: a(m) = 1: goto 510 490 if y$ = e then a(m + 2) = 1: a(m + 1) = 1: goto 510 500 if y$ = f then a(m + 2) = 1: a(m + 1) = 1: a(m) = 1 510 m=m+4 520 next n 530 next i 540 rem 550 rem perform crc algorithm on array a(0C47) 560 rem 570 for i = 0 to 31: c(i) = 1: next i 580 for n = 0 to 47 590 rem shift crc register by 1 600 for i = 32 to 1 step C1: c(l) = c(iC1): next i 610 c(0) = 0 620 t = c(32) xor a(n): rem t = control bit 630 if t = 0 then 700: rem jump if control bit=0
amd 51 AM79C90 640 c(1) = c(1) xor 1: c(2) = c(2) xor 1: c(4) = c(4) xor 1 650 c(5) = c(5) xor 1: c(7) = c(7) xor 1: c(8) = c(8) xor 1 660 c(10) = c(10) xor 1: c(11) = c(11) xor 1: c(12) = c(12) xor 1 670 c(16) = c(16) xor 1: c(22) = c(22) xor 1: c(23) = c(23) xor 1 680 c(26) = c(26) xor 1 690 c(0) = 1 700 next n 710 rem 720 rem crc computation complete, extract hash number from c(0) to c(5) 730 rem 740 hh=32*c(0)+16*c(1)+8*c(2)+4*c(3)+2*c(4)+c(5) 750 print the hash number for ; 760 print a$(0); ; a$(1); ; a$(2); ; a$(3); ; a$(4); ; a$(5); 770 print is; hh 780 goto 210 program example in c to generate the hash filter, for multicast addressing in the c-lance. /************************************************************ * hash.c rev 0.1 * generate a logical address filter value from a list of * ethernet multicast addresses. * * input: * user is prompted to enter an ethernet address in * ethernet hex format: first octet entered is the first * octet to appear on the line. lsb of most * significant octet is the first bit on the line. * octets are separated by blanks. * after results are printed, user is prompted for * another address. * * (note that the first octet transmitted is stored in * the c-lance as the least significant byte of the physical * address register.) * output: * after each address is entered, the program prints the * hash code for the last address and the cumulative * address filter function. the filter function is * printed as 8 hex bytes, least significant byte first. ****************************************************************/ #include void updatecrc (int bit); int adr[6], /* ethernet address */ ladrf[8], /* logical address filter */ crc[33], /* crc register, 1 word/bit + extra control bit */ poly[] = /* crc polynomial. poly[n] = coefficient of the x**n term of the crc generator polynomial. */ {1,1,1,0, 1,1,0,1, 1,0,1,1, 1,0,0,0, 1,0,0,0, 0,0,1,1, 0,0,1,0, 0,0,0,0 }; void main()
amd 52 AM79C90 { int k,i, byte; /* temporary array indices */ int hashcode; /* the object of this program */ char buf[80]; /* holds input characters */ for (i=0;i<8;i++) ladrf[i] = 0; /* clear log. adr. filter */ printf (enter ethernet addresses as 6 octets separated by blanks.\n); printf (each octet is one or two hex characters. the first octet \n); printf (entered is the first octet to be transmitted. the lsb of \n); printf (the first octet is the first bit transmitted. after each \n); printf (address is entered, the logical address filter contents \n); printf (are displayed, least significant byte first, with the \n); printf (appropriate bits set for all addresses entered so far.\n); printf ( to exit press the key.\n\n); while (1) { loop: printf (\nenter address: ); /* if 1st character = cr, quit, otherwise read address. */ gets (buf); if ( buf[0] == \0) break; if (sscanf (buf, %x %x %x %x %x %x, &adr[0], &adr[1], &adr[2],&adr[3],&adr[4],&adr[5]) != 6) { printf (address must contain 6 octets separated by blanks.\n); goto loop; } if ((adr[0] & 1) == 0) { printf (first octet of multicast address ); printf (must be an odd number.\n); goto loop; } /* initialize crc */ for (i=0; i<32; i++) crc[i] = 1; /* process each bit of the address in the order of transmission.*/ for (byte=0; byte<6; byte++) for (i=0; i<8; i++) updatecrc ((adr[byte] >> i) & 1); /* the hash code is the 6 least significant bits of the crc in reverse order: crc[0] = hash[5], crc[1] = hash[4], etc. */ hashcode = 0; for (i=0; i<6; i++) hashcode = (hashcode << 1) + crc[i]; /* bits 3C5 of hashcode point to byte in address filter. bits 0C2 point to bit within that byte. */ byte = hashcode >> 3;
amd 5 3 AM79C90 ladrf[byte] |= (1 << (hashcode & 7)); printf (hashcode = %d (decimal) ladrf[0:63] = , hashcode); for (i=0; i<8; i++) printf (%02x , ladrf[i]); printf ( (lsb first)\n); } } void updatecrc (int bit) { int j; /* shift crc and control bit (crc[32]) */ for (j=32; j>0; jCC) crc[j] = crc[jC1]; crc[0] = 0; /* if bit xor (control bit) = 1, set crc = crc xor polynomial. */ if (bit ^ crc[32]) for (j=0; j<32; j++) crc[j] ^= poly[j]; }
amd 54 AM79C90 table a-1 mapping of logical address to filter mask can be used to find a multicast address that maps into a particular address filter bit. for example, address bb 00 00 00 00 00 maps into bit 15. therefore, any node that has bit 15 set in its logical address filter register will re- ceive all packets addressed to bb 00 00 00 00 00. the table also shows that bit 15 is located in bit 7 of byte 1 of the logical address filter register. addresses in this table are shown in the standard ether- net format. the leftmost byte is the first byte to appear on the network with the least significant bit appearing first. table a-1. mapping of logical address to filter mask byte bit laf destination byte bit laf destination pos pos bit address accepted pos pos bit address accepted 0 0 0 8 5 0 0 0 0 0 0 0 0 0 0 4 0 3 2 2 1 0 0 0 0 0 0 0 0 0 0 0 1 1 a 5 0 0 0 0 0 0 0 0 0 0 4 1 3 3 0 1 0 0 0 0 0 0 0 0 0 0 0 2 2 e 5 0 0 0 0 0 0 0 0 0 0 4 2 3 4 4 1 0 0 0 0 0 0 0 0 0 0 0 3 3 c 5 0 0 0 0 0 0 0 0 0 0 4 3 3 5 7 1 0 0 0 0 0 0 0 0 0 0 0 4 4 4 5 0 0 0 0 0 0 0 0 0 0 4 4 3 6 e 1 0 0 0 0 0 0 0 0 0 0 0 5 5 6 5 0 0 0 0 0 0 0 0 0 0 4 5 3 7 c 1 0 0 0 0 0 0 0 0 0 0 0 6 6 2 5 0 0 0 0 0 0 0 0 0 0 4 6 3 8 8 1 0 0 0 0 0 0 0 0 0 0 0 7 7 0 5 0 0 0 0 0 0 0 0 0 0 4 7 3 9 a 1 0 0 0 0 0 0 0 0 0 0 1 0 8 2 b 0 0 0 0 0 0 0 0 0 0 5 0 4 0 8 f 0 0 0 0 0 0 0 0 0 0 1 1 9 0 b 0 0 0 0 0 0 0 0 0 0 5 1 4 1 b f 0 0 0 0 0 0 0 0 0 0 1 2 10 4b 00 00 00 00 00 5 2 42 ef 00 00 00 00 00 1 3 11 6b 00 00 00 00 00 5 3 43 cf 00 00 00 00 00 1 4 12 eb 00 00 00 00 00 5 4 44 4f 00 00 00 00 00 1 5 13 cb 00 00 00 00 00 5 5 45 6f 00 00 00 00 00 1 6 14 8b 00 00 00 00 00 5 6 46 2f 00 00 00 00 00 1 7 15 bb 00 00 00 00 00 5 7 47 0f 00 00 00 00 00 2 0 16 c7 00 00 00 00 00 6 0 48 63 00 00 00 00 00 2 1 17 e7 00 00 00 00 00 6 1 49 43 00 00 00 00 00 2 2 18 a7 00 00 00 00 00 6 2 50 03 00 00 00 00 00 2 3 19 87 00 00 00 00 00 6 3 51 23 00 00 00 00 00 2 4 20 07 00 00 00 00 00 6 4 52 a3 00 00 00 00 00 2 5 21 27 00 00 00 00 00 6 5 53 83 00 00 00 00 00 2 6 22 67 00 00 00 00 00 6 6 54 c3 00 00 00 00 00 2 7 23 47 00 00 00 00 00 6 7 55 e3 00 00 00 00 00 3 0 24 69 00 00 00 00 00 7 0 56 cd 00 00 00 00 00 3 1 25 49 00 00 00 00 00 7 1 57 ed 00 00 00 00 00 3 2 26 09 00 00 00 00 00 7 2 58 ad 00 00 00 00 00 3 3 27 29 00 00 00 00 00 7 3 59 8d 00 00 00 00 00 3 4 28 a9 00 00 00 00 00 7 4 60 0d 00 00 00 00 00 3 5 29 89 00 00 00 00 00 7 5 61 2d 00 00 00 00 00 3 6 30 c9 00 00 00 00 00 7 6 62 6d 00 00 00 00 00 3 7 31 e9 00 00 00 00 00 7 7 63 4d 00 00 00 00 00
appendix b AM79C90 55 comparison between c-lance (AM79C90) and lance (am7990) d e vices o ve r view the AM79C90 c-lance d e vice is a pin- f or-pin equiv- alent f or the am7990 lance d e vic e . using an ad- v anced 0.8-micron cmos proces s , the c-lance d e vice consumes less p o wer than the lance d e vic e , which is implemented in an outdated nmos proces s . in addition to the inherent ad v antages pr o vided b y the ad v anced cmos proces s , the c-lance d e vice in- cludes s e v eral functional enhancements o v er the lance d e vic e . the c-lance d e vice is a v aila b le in both 48-pin plastic dip and 68-pin plcc pa c kage s . these pa c kages are so c k et-compati b le with the lance pa c kage s . this document pr o vides a compa r ison of the c-lance and lance d e vice s . t a b le b-1 pr o vides a summa r y of the compa r ison between the two d e vice s . the remain- der of the document gi v es details on each item listed in t a b le b-1.
56 AM79C90 t a b le b-1. comparison summary of the c-lance and lance d e vices description AM79C90 c- lance am7990 lance 1 process/ p o wer consumption 0.8- micron cs- 21s cmos process i cc 50 ma ns- 8b nmos process i cc 270 ma 2 fifos dual fifos : 48- b yt e tx, 64- b yte rx single fifo : 48- b yt e tx/rx 3 t ransmit lo ck out due to recei v e will not occur with dual fifos and enhanced microcod e . m a y occur in high recei v e r ate situations wit h ?ess than optimal b us latencie s . 4 p er- p a c k et fcs t ransmit desc r iptor bit is used to all o w per- pa ck et addition of crc when dtcr is set in the mode registe r . no per-pa c k et crc control pr o vided. 5 ba c k off algo r ithm selecta b le modi ed ba ck off algo r ithm or standard ba ck off algo r ithm. only standard ba c k off algo r ithm a v aila b l e . 6 tx desc r iptor zero buf f er byte count capability all o w s tx b uf f er b yte count of z er o . no capability f o r tx b uf f er b yte count of z er o . 7 interfr ame spacing (ifs) beh a vior a ) implements two-pa r t de f erral after transmit b ) p a r t 1 of two-pa r t de f erral after recei v e is 6 m s c ) hea r tbeat wind o w = 4 m s d ) recei v e b lind time after recei v e less than 500 ns a ) one-pa r t de f erral after transmit b ) p a r t 1 of two-pa r t de f erral after recei v e is 4.1 m s c ) hea r tbeat wind o w = 2 m s d ) recei v e b lind time after recei v e = 4.1 m s 8 ?ea r tbeat ok (no cerr) de nition hea r tbeat ok if collision is asse r ted at a n y time from the beginning of the t r ansmission to the end of the hea r tbeat wind o w . hea r tbeat ok if collision is asse r ted du r ing the hea r tbeat wind o w . 9 recei v e lo c kup will not occu r . m a y occur when b us latency is larg e . 10 ale beh a vior ale m a y be d r i v en high at end of b us mastership when a con is set to 0 . when a con is set to 1, ale is not d r i v en l o w at end of b us mastership pe r iod. ale m a y be d r i v en l o w at end of b us mastership when a con is set to 1 . when a con is set to 0, ale is not d r i v en high at end of b us mastership pe r iod. 11 exte r nal loopba c k on a li v e netwo r k no pro b lem s . m a y recei v e i n v alid loopba c k f ailure indication s . 12 soft w are reset (s t op bit) handling a ) s t op bit in csr0 is latched . when s t op is set, the sl a v e cycle is all o wed to complete be f ore the c- lance reset s . b ) csr1 and csr2 contents are prese r v ed when the s t op bit is set to on e . a ) s t op bit in csr0 not latched and will reset the d e vice immediately when w r itten . b ) csr1 and csr2 are not prese r v ed when the s t op bit is set to on e . 13 csr0 sl a v e read data stability csr0 latched du r ing sl a v e reads to gua r antee timing on d al line s . csr0 not latched du r ing sl a v e read cycles (could gi v e timing violations on d al lines). 14 inea bit beh a vior inea bit can be set in csr0 at a n y tim e , regardless of the state of the s t op bit. inea cannot be set in csr0 while the s t op bit is set. 15 ef f ect of setting the s t op bit on csr0 bits setting the s t op bit in csr0 when the s t op bit is already set does not af f ect a n y of the other bits in csr0 (th e y are not cleared). setting the s t op bit in csr0 causes all of the other bits in csr0 to clea r , regardless of the pr e vious state of the s t op bit. 16 a c speci cation changes #06 (t tep ) maximum = 60 ns #08 (t tdp ) maximum = 60 ns #18 (t rds ) minimum = 35 ns #30 (t r d as ) minimum = 40 ns #45 (t r d ys ) minimum = 65 ns #06 (t tep ) maximum = 70 ns #08 (t tdp ) maximum = 70 ns #18 (t rds ) minimum = 40 ns #30 (t r d as ) minimum = 50 ns #45 (t r d ys ) minimum = 75 ns 17 bu r n- in option the b u r n- in option f or the c- lance is no longer a v aila b l e . 18 rx desc r iptor zero buf f er byte count handling unpredicta b le results when the rx desc r iptor buf f er byte count is set to z er o . inte r prets a bcnt eld setting of z ero in a recei v e desc r iptor as a 4096- b yte b uf f e r .
AM79C90 5 7 detailed description of enhancements 1 . p r ocess/ p o wer consumption by using an ad v anced 0.8- micron cmos proces s , the i cc speci cation f or the c-lance d e vice is reduced to 50 ma maxi m um, compared to the 270 ma maximum i cc speci cation f or the lance d e vic e . 2 . fifos the c - lance d e vice inco r porates a dual fifo (48 b yte s t r ansmit, 64 b ytes recei v e) architecture to help it compete f or bandwidth on b usy netwo r k s . the lance d e vice s single 48- b yte fifo architecture and its associated microcode has pro b lems transmitting pa c k ets out on b usy netwo r k s . this pro b lem is kn o wn as th e t ransmit lo c k out due to recei v e pro b lem . it occurs when mini m um or near-minimum ifs trafc is contin ually recei v ed b y the lance d e vice and b us la- tency is no t ?ood (?ood = latency < appr o ximately 3 m s) . in this situation, the lance d e vice s microcode and b us inter f ace is lo c k ed se r vicing recei v e pa c k et s , and is not a b le to poll the pending transmit desc r iptor (until the recei v e t r af c stops or does not pass address match) . the c - lance d e vice addresses this pro b lem b y in- cluding dual fifos and microcode that is modi ed to ta k e ad v antage of the dual fifo s . the microcode is changed so that a transmit desc r iptor poll operation oc- curs sometime ea r ly ( e xact time depends on b us laten- cies and whether the recei v e b uf f er w as o wned be f ore the recei v e pa ck et ar r i v ed) in the recei v e dma opera- tions f or each pa c k et . if the o wn bit in th e tx desc r ip- tor is f ound set, t r ansmit fifo loading dma is inte r le a v ed with the recei v e fifo emptying dma f or the pa c k et being recei v ed . the transmit pa c k et is then ready to be t r ansmitted immediately f oll o wing the end of the recei v e pa ck et on the wir e . the dual fifos and microcode changes eliminate the possibility of t r ansmit activity being lo ck ed out due to high recei v e activit y . inte r le a ving the t r ansmit dma activity with recei v e dma activity at the beginning of a reception has the ef- f ect of increasing the b us latency f or recei v e dma op- e r ation s . t o ensure that the c-lance d e vice can tole r ate the same b us latency as the lance d e vic e , the recei v e fifo in the c-lance d e vice is increased to 64 b yte s . the t r ansmit fifo in the c-lance d e vice holds 48 b yte s . 3 . t ransmit lo c k out due to receive as discussed in item 2, the dual fifo architecture and modi ed microcode implemented in the c-lance de- vice eliminates the possibility o f t ransmit lo ck out due to recei v e occur r ing. 4 . p e r - p a c ket fcs in the lance d e vic e , addition of the f rame che c k sequence (fcs or crc) to each t r ansmit pa c k et is controlled on a per-initialization basi s . in other w ord s , when the dtcr (disa b l e t ransmit crc) bit is set in the mode register at initialization, the only w a y that pa c k ets can subsequently be transmitted with an fcs attached is b y re-initializing the d e vice with the dtcr bit cleared. the c-lance d e vice pr o vides the capability to o v er- r ide the dtcr setting on a per-pa c k et basi s . if dtcr w as set in the mode register at initialization, the add_fcs bit in the transmit desc r iptor can be used to append fcs to t r ansmitted pa c k ets on a per-pa c k et basi s , o v er r iding the dtcr setting . if dtcr is cleared in the mode registe r , the add_fcs bit is a ?on? car e . the add_fcs bit is located in bit 13 o f tmd1 in the c- lance d e vic e . this bit is rese r ved in the lance d e vic e . t a b le b-2 bel o w summa r i z es the ope r ation of the add_fcs bit . note that the add_fcs bit is only meaningful in the rst desc r iptor of a transmit b uf f er chain (stp = 1). t a b le b-2. add_fcs bit operation this f eature should be compati b le with e xisting imple- mentation s . non-b r idge nodes no r mally r un with fcs ena b led (dtcr cleared) . b r idges r un with fcs dis- a b led . it is assumed that e xisting software in these applications do not set bit 13 o f tmd1 , whi c h was pr e vious l y rese r ve d . the add_fcs bit is also implemented as bit 13 of tmd1 in the pcnet-isa (am79c960) and ope r ates identically to the w a y in which it ope r ates in the c- lance d e vic e . as a side not e , this f eature can be used b y soft w are to distinguish the c - lance d e vice from the lance d e vic e . the lance d e vice w r ites bit 13 o f tmd1 to z ero when updating transmit status in the transmit desc r ipto r . the c- lance d e vice will w r ite this bit with the v alue read, so if it is set to one it will be retu r ned as a on e . dtcr in mode reg. stp add_fcs fcs added? 0 x x y es 1 0 x n/a 1 1 0 no 1 1 1 y es
58 AM79C90 5 . ba c k off algorithm a selecta b le modied ba c k off algo r ithm is pr o vided in the c - lance d e vice that can impr o v e throughput in b usy netwo r k s . bit 7 of the mode register (emba bit) is used to ena b le the modi ed ba c k off algo r ithm . this bit is rese r ved in the lance d e vic e . with the modied ba c k off algo r ithm, counting of the ifs inte r v al is suspended when recei v e car r ier sense is detected . the count resumes when recei v e car r ier sense goes a w a y . this algo r ithm increases throughput in large net w o r ks with he a vy t r af c (ma n y collisions) . it can be considered a n ?dapti v e ba c k off algo r ithm. this mode should only be used in netwo r k segments in which all nodes are using this mod e . otherwis e , the nodes that are using it will be at a disad v antage to those that are not. note: this mode does not con ict with ieee require- ments for compliance. the ieee 802.3 specication species only the minimum amount of time for the backoff interval. this leaves open the possibility of bac king off more than the minimum, which is precisely ho w the modi ed backoff algorithm works. the modi ed ba c k off algo r ithm is included as an option in the m a ce (am79c940) and pcnet-isa (am79c960) d e vice s . 6 . tx descriptor ze r o buf f er byte count capability the 12- bit bcnt eld in the t r ansmit desc r iptor of the lance and c-lance d e vices is loaded with the 2 s complement of the n umber of b ytes that m ust be t r ans- mitted from the b uf f e r . with the 2 s complement repre- sentation, a simple incrementer is used in the chip to count through the b yte count as b ytes are being read from the t r ansmit b uf f e r . when the 2 s complement n umber reaches all 0 s , the count has e xpired . the lance d e vice does not che c k f or the all 0 s case when the bcnt eld is rst loaded from the descripto r . henc e , the all 0 s case is inte r preted b y the lance de- vice as a b uf f er count of 4096 (2 12 ), pr e v enting z ero- lengt h tx b uf f ers in the lance d e vic e . in addition, the lance d e vice ignores the upper 4 bits i n tmd2, which are adjacent to the bcnt eld . these bits are indicated a s ? ust be ones in the lance data sheet. the c- lance d e vice actually uses all 16 bits i n tmd2 as the bcnt eld . compatibility with the lance de- vice is prese r v ed as long as the upper 4 bits i n tmd2 are 1 s , as specied in the lance data sheet . the c- lance d e vice che c ks f or the case where all 16 bits i n tmd2 are z ero be f ore sta r ting a n y t r ansmit dma from the b uf f e r . if all 16 bits are z er o , a z ero-length b uf f er is assumed, and the c-lance d e vice immedi- ately clears the o wn in the desc r iptor without sta r ting a n y t r ansmit activity on the net w o r k . note that since all 16 bits are che c k ed, compatibility with the lance d e vice is prese r v ed f or non-ethe r net-compliant implementation s , which m a y use b uf f er lengths of 4096 b yte s . zer o t r ansmit buf f er byte count capability is included in the pcnet- isa d e vic e . 7 . interframe spacing (ifs) beh a vior a . t w o- p a r t de f erral afte r t ransmit : t w o-pa r t de f erral after recei v e has al w a ys been an option in the ieee 802.3 speci cation . h o w e v e r , two-pa r t de f erral after t r ansmit w as recently added as an option in the 802.3 speci cation b y the ieee committe e . with two-pa r t de f erral, the ifs is divided into two pa r t s , ifs1 and ifs2 . if there is activity on the wire du r ing ifs1, the ifs counter is reset until the wire is clear again . the ifs counter is not reset once it enters ifs2 . when the ifs counter e xpire s , the chip will begin to t r ansmit if it has a n ything to send. . the speci cation s wording f or two-pa r t de f erral after transmit is identical to the w a y that t w o-pa r t de- f err al after recei v e has been worded all along . that i s , the specication species that pa r t 1 of the two pa r ts can be a n ywhere from 0 to 2/3 of the ifs (9.6 m s) . if pa r t 1 = 0 (per f ectly legal), it is equi v alent to not implementing t w o-pa r t de f erral at all . henc e , the lance d e vic e , which implements two-pa r t de- f er r al after recei v e b ut not after t r ansmit, complies with ieee specication s . h o w e v e r , implementation of t w o-pa r t de f erral after both t r ansmit and recei v e eliminates a possi b le scena r io where pa c k ets can- not be recei v ed (due to v e r y small or 0 ifs) b ut there is no indication of this f act through a collision indication at the t r ansmitte r . there f or e , although this scena r io is v e r y rar e , the c-lance d e vice im- plements t w o-pa r t de f erral after transmit in addition to after recei v e . b . the ieee 802.3 speci cations state that pa r t 1 of two-pa r t de f erral can be a n ywhere from 0 to 2/3 of the ifs (9.6 m s) . the lance d e vice only imple- ments t w o-pa r t de f er r al after recei v e , with pa r t 1 = 4.1 m s and pa r t 2 = 5.5 m s (compliant) . the c- lance d e vice implements t w o-pa r t de f erral after both t r ansmit and recei v e with pa r t 1 = 6.0 m s and pa r t 2 = 3.6 m s . since the recei v er is b linded f oll o w- ing a t r ansmit f or 4.0 m s (see bel o w), pa r t 1 of t w o- pa r t de f erral after a t r ansmit had to be e xtended be- y ond 4.1 m s or else pa r t 1 would ef f ecti v ely be only from 4.0 m s to 4.1 m s du r ing the if s . henc e , in the c- lance d e vic e , pa r t 1 of two-pa r t de f erral after tr ansmit w as set at 6.0 m s and the same v alue w as used f or pa r t 1 f oll o wing a recei v e . c . ieee 802.3 speci cations state that the signal quality error (sqe) test wind o w should be at least 4.0 m s and no more than 8.0 m s . the lance d e vice implements a 2- m s wind o w , which is not compliant with this specication . this generally tu r ns out to be a non-issue because 802.3 also species that the
AM79C90 5 9 m a u must generate the collision signal within 0.6 m s to 1.6 m s after the end of the t r ansmit pa c k et, which is typically ea r ly enough f or the lance de- vice to detect it, e v en with its non-compliant 2- m s wind o w . h o w e v e r , to comply with ieee standard s , the c- lance d e vice implements an sqe test win- d o w of 4 m s . d . ieee specications require that recei v e be b linded f oll o wing transmit f or 4 m s to pr e v ent the controller from responding to a n y t r ash that m a y be generated b y the m a u when it generates the sqe test signal. h o w e v e r , ieee specications do not state that the recei v er should be b linded f oll o wing a recei v e . the lance d e vice implements a 4.1- m s b linding time f oll o wing recei v e , violating ieee specication s . this w as erroneously implemented in the lance d e vic e , since it w as thought to be a moot issue under the assumption that there should be no v alid data on the wire within 4.1 m s of the end of a recei v e a n y w a y . h o w e v e r , since two-pa r t de f erral after transmit and recei v e are both optional, as mentioned in 7a), there are r are situations where legal pa c k ets m a y ar r i v e with an ifs of less than 4.1 m s . t o better handle this situation, the c - lance d e vice reduces the b lind time f oll o wing a recei v e to less than 500 n s . the b lind time all o ws time to store and then clear the status that w as gene r ated b y the ending reception. 8 . ?ea r tbeat ok (no cerr) denition the hea r tbeat test or signal quality error (sqe) test is per f o r med to v e r ify the ability of the a ui to pass the col- lision (sqe) indication to the dte . the lance and c-lance d e vices indicate a hea r tbeat test f ailure b y setting the cerr bit in csr0 (bit 13). at the conclusion of each transmission, the dte opens a time wind o w du r ing which it e xpects to see a collision indication . in the lance d e vic e , this wind o w begins immediately whe n tena deasse r ts and ends 2.0 m s after rena deassert s . the hea r tbeat signal is e x- pected b y the lance d e vice e v en if the pa ck et being tr ansmitted suf f ers a collision . this implementation vio- lates ieee requirements in three w a ys: 1 . ieee 802.3 specications state that the hea r tbeat wind o w should begin when the input becomes idle (rena deasse r ts), not when the output becomes idle (tena deasse r ts). 2 . if a collision occur s , the ieee 802.3 specications indicate that the dte should not look f or the sqe test signal. 3 . as mentioned in 7c), the wind o w should end no ea r lier than 4.0 m s after rena deasse r t s . the c- lance d e vice implements the hea r tbeat test in full compliance with ieee speci cation s . in the c-lance d e vic e , the hea r tbeat wind o w begins when rena deasse r ts and ends 4 m s late r . in addition, the c- lance d e vice does not look f or the hea r tbeat signal when e v er the pa c k et being transmitted suf f ers a collision. the pcnet - isa and m a ce d e vices use the same hea r tbeat ok de nition as the c- lance d e vic e . details on the lance d e vice s violations of ieee spec- i cations : the consequences of the violations of the standard b y the lance d e vice are insignicant in prac- tic e . item 1 (wind o w begins whe n tena deasse r t s , not rena) actually pr e v ents the lance from being penal- i z ed b y item 2 (hea r tbeat e xpected f oll o wing a colli- sion) . that i s , if the lance d e vice did not violate item 1 and sta r ted its wind o w when rena deasse r ted in- stead o f tena, then the lance d e vice could get f alse cerr indications when a pa c k et it is t r ansmitting suf- f ers a collision . this can happen as f oll o w s . in the e v ent of a collision, the netwo r k m a y remain acti v e f or a while after one node stops t r ansmitting its j am sequence (other nodes i n v ol v ed in the collision m a y still h a v e their j am on the wire) . at a node that ends its j am se- quence relati v ely ea r l y , the hea r tbeat signal can o v er- lap with the collision or the end of the collision frag- ment, since the m a u times the hea r tbeat signal gene r ation from when the controller stops transmitting. if this node uses a lance d e vice as its controlle r , the lance d e vice will see this hea r tbeat signal only be- cause of the violation gi v en in item 1 . if the lance d e vice sta r ted its wind o w when rena deasse r ted in- stead o f tena, it w ould miss the hea r tbeat signal, since the hea r tbeat passes b y while the collision is still on the wir e . this would gi v e f alse cerr indication s . henc e , the violation of item 1 in the lance d e vice is not a pro b lem . in f act, it ma k es the violation of item 2 gene r ally a non- issu e . although the violation of item 1 masks the violation of item 2 as just desc r ibed, the violation of item 2 (hea r t- beat still e xpected b y the lance d e vice when collision occurs) can still lead to f alse cerr indications when the lance d e vice is used with a non-802.3-compliant m a u . the ieee 802.3 specications state that the m a u is to gene r ate the sqe test signal after e v e r y t r ansmit, e v en when the t r ansmit suf f ers a collision . h o w e v e r , some m a us on the ma r k et h a v e been f ound not to comply with this requirement . when ope r ating with a non-compliant m a u that does not generate the hea r t- beat signal after a collided t r ansmission, the lance d e vice can gi v e f alse cerr indication s . as mentioned in 7c), item 3 is generally a non-issu e . 9 . receive lo c kup the lance d e vice has an er r atum in which the re- cei v er lo c ks up when the system b us latency is v e r y high . this er r atum is x ed in the c- lance d e vic e .
6 0 AM79C90 10 . ale beh a vior the lance d e vice m a y d r i v e the ale pin l o w at the end of each b us mastership pe r iod when a con = 1 (ale/as acti v e l o w?s mode) . when the b us master- ship period end s , the ale pin is t r i-stated ; henc e , if ale is pulled high b y e xte r nal logi c , a glitch on ale result s . the glitch occurs about when the lance de- vice is releasing the b us b y b r inging hold high . the c- lance d e vice inco r po r ates redesigned ale logic to pr e v ent this glitch from occur r ing. h o w e v e r , in the c-lance, when a con = 0 (acti v e high ale), ale is dri v en high be f ore it is t r i-stated at the end of e v e r y b us mastership pe r iod . in the lance, when a con = 0 (acti v e high ale), ale is not d r i v en high be f ore it is t r i-stated at the end of e v e r y b us mas- tership pe r iod. this dif f erence will not cause a n y pro b lems in designs that set a con = 1 (as ; acti v e l o w ale) . it could cause pro b lems in designs in which a con = 0 . the ale sig- nal is intended to pr o vide a strobe signal f or an e xte r nal address latch . the r ising edg e , coupled with a subse- quent f alling edge that will occur if the pin is e xte r nally pulled d o wn, will cause an i n v alid address to be strobed into the e xte r nal address latch . h o w e v e r , since this occurs at the end of the b us mastership pe r iod, and fu r ther master cycles are not per f o r med b y the c - lance subsequent to the i n v alid address being strobed (until the n e xt b us mastership pe r iod), the in- v alid address generally has no ef f ect . a design could h a v e pro b lems with this if e xte r nal logic is conti n uously decoding the latched address and taking some action on it e v en though the c-lance is not e x ecuting a n y master cycle s . 11 . external loopba c k on a live net w ork the lance d e vice has an erratum that causes loop- ba c k f ailures when e xte r nal loopba c k is r un on a li v e netwo r k . this er r atum is x ed in the c- lance d e vic e . 12 . software reset (s t op bit) handling a . latching of the s t op bit : in the lance d e vic e , w r it- ing the s t op bit in csr0 causes all b us signals to immediately oat . with read y pulled up e xte r nally ( read y is open d r ain), this causes read y to deas- se r t prematurely du r ing the sl a v e cycl e . if d as and cs remain acti v e , the lance d e vice can errone- ously sta r t another sl a v e cycl e . the c- lance de- vice latches the s t op bit and, when it is set, all o ws the sl a v e cycle in progress to complete be f ore re- setting the pa r t. b . prese r v ation of csr1 and csr2 : the lance de- vice does not prese r v e the contents of csr1 and csr2 du r ing the initialization proces s . henc e , when the s t op bit is set, the contents of csr1 and csr2 are not the same as th e y were be f ore initial- ization and th e y must be r e w r itten be f ore re - initializing . this is not really a pro b lem in the lance d e vic e , b ut it can add e xtra inst r uctions to soft w ar e . the c-lance d e vice rem o v es this soft- w are b urden b y prese r ving the contents of csr1 and csr2 during initialization so that when the s t op bit is set, th e y do not h a v e to be reloaded be- f ore re- initializing . not e , h o w e v e r , that if the de f ault v alues of csr3 (de f aults f or bcon, a con, and bswp are 0, 0, and 0, respecti v ely) are not used, csr3 must still be reloaded after setting the s t op bit in the c-lance d e vic e , since csr3 is cleared when the s t op bit is set. 13 . csr0 sl a ve read data stability in the lance d e vic e , the status bit latches in csr0 m a y change at a n y tim e , as g o v e r ned b y the occur- rence of the e xte r nal e v ents th e y monito r . henc e , the err, babl, cerr, mis s , idon, and intr bits in csr0 m a y change du r ing a sl a v e read cycle in which th e y are being accessed . this can cause timing viola- tions on the d al line s . in the c-lance d e vic e , csr0 is latched in a shad o w register during a read so that timing on the d al lines is guaranteed. 14 . inea bit beh a vior with the c-lance d e vic e , an inea bit can be set in csr0 at a n y tim e , regardless of the state of the s t op bit . this actually rem o v es a rest r iction that w as present in the lance d e vic e , in which the inea bit in csr0 could be not be set while the s t op bit w as set. this dif f erence bet w een the t w o d e vices does not af f ect no r mal d e vice ope r ation, b ut could dis r upt diagnostic code w r itten f or the lance d e vic e . 15 . effect of setting the s t op bit on csr0 bits in the lance d e vic e , csr0 is reset when the s t op bit in csr0 is set . this reset happens e ven if the s t op bit was alrea d y set. when the reset occur s , all of the other bits in csr0 are cleared . in the c-lance, csr0 is reset when the s t op bit is set in csr0 o n l y if the s t op bit was not alrea d y set. this dif f erence bet w een the t w o d e vices does not af f ect no r mal d e vice ope r ation, b ut could dis r upt diagnostic code w r itten f or the lance d e vic e . 16 . a c speci cation changes the f oll o wing dif f erences in a c specication e xist betw een the c- lance and the lance. c- lance lance #06 (t tep ) maximum 60 ns 70 ns #08 (t tdp ) maximum 60 ns 70 ns #18 (t rds ) minimum 35 ns 40 ns #30 (t r d as ) minimum 40 ns 50 ns #45 (t r d ys ) minimum 65 ns 75 ns
AM79C90 6 1 17 . elimination of burn-in option the b u r n- in option f or the c-lance is no longer a v ail- a b l e . thu s , the orde r ing pa r t number AM79C90pcb is no longer v alid (see page 4 of the c-lance data sheet). 18 . rx descriptor ze r o buffer byte count handling the 12-bit bcnt eld in the recei v e desc r iptor of the lance and c-lance d e vices is loaded with the 2 s complement of the n umber of b ytes allocated to the associated recei v e b uf f e r . in the lance d e vic e , when all 0 s are w r itten to the bcnt eld in a recei v e desc r ip- to r , a b uf f er length of 4096 (2 12 ) b ytes is assumed . in the c-lance d e vic e , the case of all 0 s in the recei v e desc r iptor m a y produce unpredicta b le result s . this dif f erence should not cause pro b lems in ieee 802.3-compliant netwo r k s , because 802.3 has a maxi- m um pa ck et length speci cation of 1518 b yte s .
trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identitcation purposes only and may be trademarks of their respective companies.

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